Active-matrix substrate and method of fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...

Reexamination Certificate

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C257S059000, C257S060000, C257S061000, C257S072000, C257S074000, C257S070000, C257S071000

Reexamination Certificate

active

06774399

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active-matrix substrate used for Liquid-Crystal Display (LCD) devices, and a method of fabricating the same. More particularly, the invention relates to an active-matrix substrate comprising a dielectric plate and switching elements such as Thin-Film Transistors (TFTs) arranged in a matrix array on the plate, and a method of fabricating the substrate.
2. Description of the Related Art
In recent years, active-matrix addressing LCD devices using TFTs as their switching elements have been developed and used practically. LCD devices of this type comprise typically an active-matrix substrate on which gate lines, drain lines and TFTs are regularly arranged; an opposite substrate on which a color filter and a black matrix are formed; and a layer of liquid crystal sandwiched by the active-matrix substrate and the opposite substrate. On operation, a proper voltage is applied across the electrodes formed on the active-matrix substrate and the corresponding electrode or electrodes formed on the opposite substrate, or across the relating electrodes formed on the active-matrix substrate. Thus, the molecules of the liquid crystal are rotated to the specific orientations at the respective pixels according to the applied voltage to thereby change the transmission/reflection characteristic of light at the pixels, thereby displaying desired images on the screen of the LCD device.
With active-matrix addressing LCD devices, it is important to strictly control the orientation of the molecules of the liquid crystal to generate desired high-resolution and high-quality images. To realize this, it is required to enhance the accuracy of substrate flatness, electrode shape, electrode intervals, and so on.
FIG. 1
shows the structure of a prior-art active-matrix substrate of the LCD device of this type, which is fabricated in the following way. Although the substrate actually comprises TFTs, gate lines, and data lines, only one of the TFTs is shown in
FIG. 1
for the sake of simplification.
First, a semiconductor layer, which is typically made of amorphous silicon or polycrystalline silicon, is formed on a transparent glass plate
101
and then, it is patterned by using popular photolithography and dry-etching techniques, forming semiconductor islands
112
on the plate
101
.
Nest, a silicon dioxide (SiO
2
) layer
117
a
is formed on the whole surface of the plate
101
to cover the semiconductor islands
112
and patterned, thereby forming gate dielectric layers
117
a
on the islands
112
for the respective TFTs
102
. The remaining layer
117
covers the surface of the plate
101
.
A conductive layer is formed to cover the SiO
2
layer
117
and the gate dielectric layers
117
a
over the whole plate
101
and patterned, thereby forming gate electrodes
107
a
and gate lines (not shown in FIG.
1
). The gate lines are connected to the respective electrodes
107
a
. In other words, specific parts of each gate line serve as the gate electrodes
107
a.
Proper dopant atoms are selectively introduced into the semiconductor islands
112
in self-alignment with respect to the corresponding gate electrodes
107
a
by the ion-implantation method, thereby forming a source region and a drain region in each of the islands
112
. The remaining part of each island
112
between the source and drain regions, which is located below the gate electrode
107
a
, forms a channel region.
A silicon nitride (SiN
x
) layer
118
is formed on the SiO
2
layer
117
a
to cover the gate electrodes
107
a
and the gate lines over the whole plate
101
. The layer
118
serves as an interlayer dielectric layer. Then, the layer
118
is selectively removed by the etching method in the peripheral area of each of the islands
112
, thereby forming two contact holes that expose the source and drain regions or each island
112
by way of the SiO
2
and SiN
x
layers
117
and
118
, respectively.
A conductive layer is formed on the interlayer dielectric layer
118
of SiN
x
over the whole plate
101
and patterned, thereby forming a source electrodes
108
a
and a drain electrode
108
b
for each of the TFTs
102
, and data lines (not shown in
FIG. 1
) over the plate
101
. The data lines are connected to the corresponding source electrodes
108
a
of the TFTs
102
. Each of the source electrodes
108
a
is contacted with the source region of the semiconductor island
112
by way of its contact hole. Each of the drain electrodes
108
b
is contacted with the drain region of the island
112
by way of its contact hole.
Through the above-described process steps, the ThTs
102
, the gate lines, and the data lines are fanned on the plate
101
.
Subsequently, a thick, transparent, dielectric planarization layer
106
is formed on the interlayer dielectric layer
118
to cover the TFTs
102
and the gate and data lines. Contact holes
116
are formed to penetrate the layer
106
at the locations just above the respective source electrodes
108
a
. These contact holes
116
are to expose the underlying source electrodes
108
a
from the layer
106
.
A transparent conductive layer such as Indium Tin Oxide (ITO) is formed on the planarization layer
106
and patterned, thereby forming pixel electrodes
109
in the respective pixel regions on the layer
106
. Each of the pixel electrodes
109
is contacted with a corresponding one of the source electrodes
108
a
of the TFT
102
by way of its contact hole
116
of the planarization layer
106
.
Thus, the prior-art TFT substrate of
FIG. 1
is fabricated.
On the other hand, a color filter for red (R), green (G) and blue (B) colors and a black matrix for blocking unnecessary light among the pixels are formed on a transparent glass plate. Thus, an opposing substrate is formed.
Following this, the active-matrix substrate and the opposing substrate are fixed together to keep a specific gap between them with spacers. A specific liquid crystal is filled into the gap and sealed. Thus, the active-matrix LCD device is fabricated.
With the above-described prior-art active-matrix substrate of
FIG. 1
, the planarization layer
106
is formed to reduce the height difference between the areas including the TFT
102
and the gate and data lines and the other area. However, there is a problem that the height difference is not sufficiently reduced as desired with the use of the layer
106
.
In particular, each pixel electrode
109
is raised at its end part
109
a
near the corresponding TFT
102
with respect to the surface of the plate
101
corresponding to the surface inclination of the layer
106
, as shown in FIG.
1
. Therefore, the gap between the active-matrix substrate of FIG.
1
and the opposing substrate varies and therefore, the voltage applied across these two substrates becomes non-uniform. This results in a problem of degradation of image quality. This problem is caused by the fact that the TFTs
102
(and the gate and data lines) generate protrusions of the planarization layer
106
and at the same time, each of these protrusions is considerably wide.
To solve the above-described problem, the inventor created the following improvement and submitted it as a Japanese patent application.
Specifically, prior to the formation of the TFTs, a transparent dielectric layer is selectively formed on a transparent plate except for the areas for the TFTs and the gate and data lines. The transparent dielectric layer has a thickness equal to or greater than the height difference between the areas including the TFTs and the gate and data lines and the other area. With this technique, the area for each pixel electrode is planarized by the transparent dielectric layer and therefore, the above-identified problem can be solved.
The structure of the active-matrix substrate and a method of fabricating the same according to the above-described inventor's improvement are explained below with reference to
FIGS. 2A
to
2
C.
FIG. 2C
is a plan view showing the arrangement of the pixels including the TFTs, the gate a

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