Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2001-08-24
2004-09-28
Tran, Thien F (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S088000
Reexamination Certificate
active
06797982
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix substrate and a method of making the substrate and also relates to a display device including the active matrix substrate and a method for fabricating the display device.
Recently, liquid crystal display devices (LCDS) have been further broadening their applications. LCDs were normally used indoors as image display devices for desktop computers or TV sets. But now LCDs are often used as video or information display devices for various types of mobile electronic units including cell phones, notebook or laptop computers, portable TV sets, digital cameras and digital camcorders and for car-mounted electronic units like a car navigation system.
Some types of LCDs are addressed using matrix electrodes. Those matrix-addressed LCDs are roughly classifiable into the two categories of passive- and active-matrix-addressed LCDs. In an active-matrix-addressed LCD, pixels are arranged in columns and rows as its name signifies, and each of those pixels is provided with a switching element. And by controlling those switching elements using data and gate lines that are arranged to cross each other, the LCD of this type can supply desired signal charge (i.e., data signal) to a selected one of the pixel electrodes.
Hereinafter, a known active-matrix-addressed LCD will be described with reference to
FIGS. 43 and 44
.
FIG. 43
illustrates a schematic configuration for a known LCD of that type.
FIG. 44
illustrates a cross-sectional structure for a typical liquid crystal panel.
As shown in
FIG. 43
, the LCD includes liquid crystal panel
50
and gate and source drive circuits
51
and
52
with gate and source drivers
53
. The panel
50
spatially modulates incoming light. The gate drive circuit
51
selectively drives switching elements in the liquid crystal panel
50
, while the source drive circuit
52
supplies a signal to each pixel electrode in the panel
50
.
As shown in
FIG. 44
, the panel
50
includes: a pair of transparent insulating substrates
54
and
55
of glass; a liquid crystal layer
38
interposed between the substrates
54
and
55
; and a pair of polarizers
56
placed on the outer surfaces of the substrates
54
and
55
. The liquid crystal layer
38
may be a twisted nematic liquid crystal layer, for example.
On the inner surface of the substrate
54
facing the liquid crystal layer
38
, pixel electrodes
114
are arranged in matrix. A common transparent electrode
36
is formed on the inner surface of the substrate
55
. In this construction, a desired voltage can be applied to a selected part of the liquid crystal layer
38
using the pixel electrodes
114
and common transparent electrode
36
. Each of the pixel electrodes
14
is connected to the source drive circuit
52
by way of its associated thin-film transistor (TFT)
110
and data line (not shown in FIG.
44
). As shown in
FIG. 44
, the TFTs
110
are formed on the substrate
54
. The switching operation of the TFTs
110
is controllable using gate lines (not shown in
FIG. 44
, either), which are connected to the gate drive circuit
51
and formed on the substrate
54
.
On the inner surface of the substrate
55
facing the liquid crystal layer
38
, black matrix
35
, R, G and B color filters and common transparent electrode
36
have been formed.
The inner surface of the substrates
54
and
55
facing the liquid crystal layer
38
is covered with an alignment film
37
. And in the liquid crystal layer
38
, spacers
40
with a size of several &mgr;m are dispersed.
The substrate
54
including these members thereon is collectively called an “active matrix substrate”, while the substrate
55
with those members thereon is called a “counter substrate”.
Hereinafter, various structures for known active matrix substrates will be described.
FIG. 45A
illustrates a layout for a unit pixel region defined for a known active matrix substrate, while
FIG. 45B
illustrates a cross section of the unit pixel region taken along the line A-A′ shown in FIG.
45
A.
In the example illustrated in
FIGS. 45A and 45B
, multiple gate lines
102
and multiple data lines
105
are formed over a glass substrate
121
so as to cross each other. More specifically, the gate lines
102
belong to a first layer on the glass substrate
121
, while the data lines
105
belong to a second layer located over the first layer. And the gate and data lines
102
and
105
are electrically isolated from each other by an insulating film
104
belonging to a third intermediate layer between the first and second layers.
In each rectangular region surrounded by the gate and data lines
102
and
105
, a pixel electrode
114
has been formed by patterning a transparent conductive film, for example. The pixel electrode
114
receives signal charges from associated one of the data lines
105
by way of a TFT
110
that has been formed near the intersection between the associated data line
105
and one of the gate lines
102
. A storage capacitance line
113
has been formed under the pixel electrode
114
to extend parallel to the gate lines
102
. Accordingly, a storage capacitance is created between the pixel electrode
114
and storage capacitance line
113
.
As shown in
FIG. 45B
, the TFT
110
includes gate electrode
103
, gate insulating film
104
, intrinsic (i-) semiconductor layer
106
, doped semiconductor layer
107
and source/drain electrodes
108
and
109
. The gate electrode
103
is a branch extended vertically from the gate line
102
as shown in FIG.
45
A. The gate electrode
103
is covered with the gate insulating film
104
. The semiconductor layer
106
is located right over the gate electrode
103
with the gate insulating film
104
interposed therebetween. The doped semiconductor layer
107
exists on the i-semiconductor layer
106
. And the source/drain electrodes
108
and
109
are electrically connected to source/drain regions defined in the i-semiconductor layer
106
by way of the doped semiconductor layer
107
. As shown in
FIG. 45A
, the source electrode
108
is a branch extended vertically from the data line
105
and forms part of the data line
105
.
The drain electrode
109
is a conductive member that electrically connects the drain region of the TFT
110
and the pixel electrode
114
together. The drain electrode
109
, as well as the data lines
105
and source electrode
108
, is formed by patterning a metal film. That is to say, in the illustrated example, the data lines
105
and source/drain electrodes
108
and
109
belong to the same layer, and their layout is determined by a mask pattern for use in a photolithographic process.
The source/drain electrodes
108
and
109
are connected together via a channel region defined in the i-semiconductor layer
106
. And the electrical continuity of the channel region is controllable by the potential level at the gate electrode
103
. Where the TFT
110
is of n-channel type, the TFT
110
can be turned ON by raising the potential level at the gate electrode
103
to the inversion threshold voltage of the transistor
110
or more. Then, the source/drain electrodes
108
and
109
are electrically continuous to each other, thereby allowing charges to be exchanged between the data line
105
and pixel electrode
114
.
To operate the TFT
110
properly, at least part of the source/drain electrodes
108
and
109
should overlap with the gate electrode
103
. Normally, the gate electrode
103
has a line width of about 10 &mgr;m or less. Accordingly, in a photolithographic process for forming the data lines
105
and source/drain electrodes
108
and
109
, these members
105
,
108
and
109
should be aligned accurately enough with the gate electrode
103
already existing on the substrate
121
. Normally, an alignment accuracy required is on the order of ± several micrometers or even less.
Also, the size of the area where the gate and drain electrodes
103
and
109
overlap with each other defines a gate-drain capacitance C
gd
, which is one of key parameters deter
Ban Atsushi
Ohgami Hiroyuki
Okada Yoshihiro
Okamoto Masaya
Saito Yuichi
Conlin, Esq. David G.
Edwards & Angell LLP
Konieczny J. Mark
Sharp Kabushiki Kaisha
Tran Thien F
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