Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Patent
1994-12-06
1996-10-08
Limanek, Robert P.
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
257351, 257408, 437 27, 437 28, 437 29, H01L 2701, H01L 2904, H01L 2976
Patent
active
055634273
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin-film transistor, an active matrix circuit board or active matrix panel, and a manufacturing method thereof. More particularly, the present invention relates to a technology improving the electrical characteristics of the thin-film transistor.
2. Description of the Related Art
Thin-film transistors (hereafter "TFT") which use a polycrystalline silicon film are used as pixel transistors in liquid crystal display panels and other active matrix circuit boards. Of the available liquid crystal display panels, active matrix circuit boards with integrated drive circuits (integrated peripheral circuits) which are formed using TFTs in the area peripheral to the pixel area are used in, for example, relatively small liquid crystal display panels for viewfinders and projectors because it is difficult to make electrical connections to narrow pitch terminals by using conventional assembly technology. As a result, drive circuit TFTs and pixel TFTs must both be formed on the same active matrix circuit board.
Of these TFTs, a low OFF current is required in the TFT of the pixel area so that the charge written through the pixel electrodes can be maintained. Polycrystalline silicon TFTs, however, may use an offset gate structure wherein a source-drain region is provided at a position separated from the edge of the gate electrodes due to a high OFF current.
In addition, a lightly doped region (LDD region) may be provided at the edge of the drain region in order to reduce the electrical field strength therein.
The following manufacturing method is conventionally used to manufacture thin-film transistors with such a structure.
FIGS. 40-40B depict the formation of an n-channel type TFT 1200a in the drive circuit area, p-channel type TFT 1200b in the drive circuit area, and n-channel type TFT 1200c in the pixel area from left to right facing the figure. First, second, and third silicon films 1201, 1202, 1203 are first formed on the surface side of substrate 1201. The surface sides of the first, second, and third silicon films 1201, 1202, 1203 are then covered by gate insulation film 1211. After that, a conductive film which can comprise the gate electrode is formed on the surface side of the gate insulation film 1211. This conductive film, in turn, is etched using resist layer 1213 for a mask and results in formation of gate electrode 1212.
Next, as indicated by arrow 1214, impurity ions representing donors are implanted, and source-drain area 1207 is formed. Gate electrode 1212 is over-etched with resist 1213 as the mask, and gate electrode 1212 is narrowed as shown in FIG. 40B. As a result, the length of gate electrode 1212 is shorter than the length of the region (channel region) in first, second, and third silicon films 1202, 1202, 1203 in which impurity ions are not, and the offset gate structure is formed.
Next, as shown in FIG. 40C, impurity implanted ions representing the acceptors are implanted (arrow 1221) to second silicon film 1202 with first and third silicon films 1201, 1203 covered by resist 1215. As a result, source-drain region 1209 is formed. In this case, since the donor impurity was previously implanted to second silicon film 1202, the dose of acceptor impurity is much higher than the concentration of donor impurity implanted in the second film.
Note that when TFTs 1200a and 1200c are formed with an LDD structure, resist 1215 is removed after implanting acceptor and donor impurity at their appropriate respective doses. IN the TFT having the offset or LDD structure thus formed, the OFF current can be sufficiently lowered because the electrical field strength at the drain edge can be reduced.
The following problems exist with the conventional manufacturing method thus described, however.
First, even though TFT electrical characteristics vary with the gate length, this method sets the gate length by over-etching the gate electrode, and it is therefore difficult to control the gate length. For example, when a gate electrod
REFERENCES:
patent: 5141885 (1992-08-01), Yoshida et al.
patent: 5250931 (1993-10-01), Misawa et al.
patent: 5323042 (1994-06-01), Matsumoto
patent: 5393992 (1995-02-01), Suzuki
patent: 5396084 (1995-03-01), Matsumoto
patent: 5396099 (1995-03-01), Kitajima
Matsuo Minoru
Takenaka Satoshi
Yudasaka Ichio
Hardy David B.
Johnson W. Glen
Limanek Robert P.
Seiko Epson Corporation
LandOfFree
Active matrix panel and manufacturing method including TFTs havi does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Active matrix panel and manufacturing method including TFTs havi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Active matrix panel and manufacturing method including TFTs havi will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-59530