Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-09-25
2001-05-22
Hjerpe, Richard A. (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06236379
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix panel with a built-in data line drive circuit and to a display device using the panel.
2. Description of the Related Art
On an active matrix panel in which a polycrystal silicon is used for a channel of a thin film transistor (hereinafter referred to as TFT), pixel electrodes and TFTs for picture element which are provided correspondingly to the electrodes are arranged in the form of matrix, and a plurality of data lines and scanning lines are arranged according to the TFTs also in the form of matrix. A built-in drive circuit for supplying data signals and scanning signals to the data lines and the scanning lines is provided in the same active matrix panel on which the pixel TFTs are formed.
Examples of such built-in type conventional data line drive circuits are shown in
FIGS. 1 and 2
. In a data line drive circuit
1
as shown in
FIG. 1
, a series of RGB color video signals are input to the circuit which is composed of three color video signal lines
1
R,
1
G, and
1
B for leading a series of RGB color video signals in a panel; switching elements
11
,
21
,
31
. . . for connecting data lines D
1
, D
4
, D
7
. . . to the color video signal line
1
R; switching elements
12
,
22
,
32
. . . for connecting data lines D
2
, D
5
, D
8
. . . to the color video signal line
1
G; switching elements
13
,
23
,
33
. . . for connecting data lines D
3
, D
6
, D
9
. . . to the color video signal line
1
B; and a drive pulse generating circuit comprising a shift register
4
for sequentially generating drive pulses PA
1
, PA
2
, PA
3
. . . in response to clock signals CLKS. The drive pulse PA
1
at the first stage of the shift register
4
is applied to the switching elements
11
,
12
, and
13
, then the drive pulse PA
2
at the next stage is applied to the switching elements
21
,
22
, and
23
, and subsequently same processes are repeated, in other words, the respective identical drive pulses are applied to each three switching elements corresponding to the BRG color video signals.
At the exterior of the panel, as shown in
FIG. 3
, are provided a sample hold circuit
100
for a series of RGB color video signals which sequentially performs sampling of each RGB color video signal and simultaneously output hold signals for a prescribed period, and an inversion amplifier
200
which amplifies each of the RGB signals having gone through sample hold and outputs the signal after inverting it at every horizontal period and vertical period. It is arranged so that three outputs of the inversion amplifier
200
are input to the three color video signal lines
1
R,
1
G, and
1
B in the panel.
Thus, when the drive pulse PA
1
becomes high level, the switching elements
11
,
12
, and
13
, which correspond to a series of RGB signals equivalent to three dots, are simultaneously turned on. Then, video signals input to the three color video signal lines
1
R,
1
G, and
1
B are simultaneously supplied to the data lines D
1
, D
2
, and D
3
. Similarly, when the drive pulses PA
2
, PA
3
. . . Sequentially become high level, respective RGB video signals equivalent to three dots are simultaneously supplied to the data lines.
Here, the video signal lines
1
R,
1
G, and
1
B have various parasitic capacities and line resistance, whereby video signals are delayed. In a circuit of a three dot corresponding system as shown in
FIG. 3
, new video signals are input to each of the video signal lines at intervals of three dots from an external sample hold circuit. Thus, for example, when a video signal three dots before is black level and a video signal three dots after is white level, when a delay of the video signal is great, a part of the black level is mixed with the white level three dots later, whereby a ghost of intermediate level may arise.
Such a ghost is negligible in displaying ordinary analog video signals for television or the like, but is very conspicuous when the display is used for displaying graphics. Thus, a circuit shown in
FIG. 2
is occasionally used to prevent such ghosts from appearing.
A data line drive circuit
2
for inputting two series of RGB color video signals as shown in
FIG. 2
is composed of six color video signal lines
1
R,
1
G,
1
B,
2
R,
2
G, and
2
B for leading two series of RGB color video signals in the panel; switching elements
11
,
31
. . . for connecting data lines D
1
, D
7
. . . to the color video signal line
1
R; switching elements
12
,
32
. . . for connecting data lines D
2
, D
8
. . . to the color video signal line
1
G; switching elements
13
,
33
. . . for connecting data lines D
3
, D
9
. . . to the color video signal line
1
B; switching elements
21
,
41
. . . for connecting data lines D
4
, D
10
. . . to the color video signal line
2
R; switching elements
22
,
42
. . . for connecting data lines D
5
, D
11
. . . to the color video signal line
2
G; switching elements
23
,
43
. . . for connecting data lines D
6
, D
12
. . . to the color video signal line
2
B; and a drive pulse generating circuit comprising a shift register
5
for sequentially generating drive pulses PB
1
, PB
2
, PB
3
. . . in response to clock signals CLKs. The drive pulse PB
1
at the first stage of the shift register
5
is applied to the switching elements
11
,
12
,
13
,
21
,
22
, and
23
, then the drive pulse PB
2
at the next stage is applied to the switching elements
31
,
32
,
33
,
41
,
42
, and
43
, and subsequently same processes are repeated, in other words, the respective identical drive pulses are applied to each six switching elements corresponding to two series of RGB color video signals.
When graphics are displayed, a video signal to be input is typically an 8-bit-per-dot digital signal. At the exterior of the panel, there are provided a sample hold circuit
300
for two series of RGB signals which sequentially perform sampling of each series of RGB color video signals and simultaneously output hold signals equivalent to six dots for a prescribed period, a D/A converter
400
for converting digital signals equivalent to six dots supplied from the sample hold circuit
300
into analog signals, and an inversion amplifier
500
which amplifies the converted analog signals equivalent to six dots and outputs the signals after inverting them at every horizontal period and vertical period. It is arranged so that six outputs of the amplifier
500
are input to the six color video signal lines
1
R,
1
G,
1
B,
2
R,
2
G, and
2
B in the panel.
Thus, when the drive pulse PB
1
becomes high level, the switching elements
11
,
12
,
13
,
21
,
22
, and
23
which correspond to two series of RGB color video signals equivalent to six dots are simultaneously turned on, and video signals input to the six color video signal lines
1
R,
1
G,
1
B,
2
R,
2
G, and
2
B are then supplied simultaneously to the data lines D
1
, D
2
, D
3
, D
4
, D
5
, and D
6
. Similarly, when the drive pulses PA
2
, PB
3
. . . sequentially become high level, respective RGB video signals equivalent to six dots are simultaneously supplied to the data lines.
With this constitution, new video signals are input to each of the video signal lines from an external sample hold circuit at intervals of six dots. Thus, even when a video signal six dots before is black level, a video signal six dots later is white level, and a delay of video signals is great, a part of the black level will not mix with the white level and ghost images can be prevented. Thus, such constitution of six dots corresponding system is optimum when graphic images are displayed.
As described above, a conventional three dots system circuit such as is shown in
FIG. 1
is not sufficient for displaying graphics because such ghosts will arise. However, ghosts can be ignored when ordinary analog video signals are displayed and in such a system it is sufficient to have a series of external sample hold circuit. Thus, conventional circuit have advantages in terms of cost. On the other hand,
Kobayashi Mitsugu
Yokoyama Ryoichi
Hjerpe Richard A.
Hogan & Hartson LLP.
Laneau Ronald
Sanyo Electric Co,. Ltd.
LandOfFree
Active matrix panel and display device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Active matrix panel and display device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Active matrix panel and display device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2498760