Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-02-10
2003-05-13
Mengistu, Amare (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S092000, C345S095000, C345S098000, C345S099000, C345S103000, C345S208000
Reexamination Certificate
active
06563481
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix liquid crystal display device, a method of manufacturing the same, and a method of driving the same suitable for a liquid crystal display device of an active matrix type.
2. Description of the Prior Art
A liquid crystal display panel for a conventionally general active matrix liquid crystal display device is expressed by an equivalent circuit shown in FIG.
1
. More specifically, gate bus lines G
1
to G
4
and drain bus lines D
1
to D
4
are arranged to perpendicularly intersect each other, and a transistor
1
and a display pixel
2
are connected to each of their intersections. Each display pixel
2
is connected to a common electrode
3
.
This active matrix liquid crystal display device is driven by drive signals shown in
FIG. 3
in order to display a display pixel array dij (i, j=1, 2, 3, . . . ) as shown in FIG.
2
. More specifically, one of the gate bus lines G
1
to G
4
is set at high level to turn on the corresponding transistors, and data on the drain bus lines D
1
to D
4
are written in the corresponding display pixels. This operation is sequentially performed for the gate bus lines G
1
to G
4
, so that the liquid crystal display panel performs display with its display pixels.
In this manner, in the conventionally general active matrix liquid crystal display device, one drain bus line driving driver is required for each intersection of the gate bus lines G
1
to G
4
and drain bus lines D
1
to D
4
arranged to form a matrix.
Since the drain bus line driving driver covers a wide frequency range such as that of an image signal and operates at a high data rate, it is expensive. When the number of display pixels increases, a large number of expensive drain bus line driving drivers must be used, and the resultant liquid crystal display device becomes expensive.
In order to eliminate these drawbacks, for example, Japanese Unexamined Patent Publication Nos. 3-38689, 6-148680, and 4-269791 disclose the following techniques.
The outline of the technique of Japanese Unexamined Patent Publication No. 3-38689 will be described with reference to
FIGS. 4
to
6
.
FIG. 4
is an equivalent circuit diagram of a liquid crystal panel,
FIG. 5
is a view showing the display data arrangement, and
FIG. 6
is a timing chart for displaying the data arrangement of FIG.
5
.
Referring to
FIG. 4
, two columns of display pixels are connected to one drain bus line D
1
or D
2
, and gate bus lines G
1
to G
8
are connected to the transistors on one drain bus line D
1
or D
2
.
In this case, as shown in
FIG. 6
, the gate potentials of the gate bus lines G
1
, G
3
, G
5
, and G
7
are set at high level and subsequently the gate potentials of the gate bus lines G
2
, G
4
, G
6
, and G
8
are set at high level, so that the transistors aligned on the bus line are turned on. Data on the drain bus line D
1
or D
2
is written in the display pixel at this ON timing.
As shown in
FIG. 5
, on the drain bus line D
1
, data are written in d
11
, d
21
, d
31
, and d
41
on the first display pixel column, and subsequently in d
12
, d
22
, d
32
, and d
42
on the second display pixel column. Data write is performed on the other drain bus line D
2
in the same manner.
According to this method, one drain bus line D
1
or D
2
can drive two display pixel columns. As a result, the number of drivers for the drain bus lines D
1
and D
2
can be halved, so that the product cost can be reduced.
The technique shown in Japanese Unexamined Patent Publication No. 6-148680 also aims at reduction of the product cost by increasing the number of gate bus lines while decreasing the number of expensive drain bus lines.
The outline of the technique shown in Japanese Unexamined Patent Publication No. 4-269791 will be described with reference to the equivalent circuit diagram of the liquid crystal panel shown in FIG.
7
.
Display signal electrodes that form a liquid crystal signal-side drive circuits have transfer gates QT, driving transfer gates Q, and capacitors CL serving as line memories in units of columns. Each of display signal terminals VD
1
to VD
40
is connected to either the source electrodes or drain bus lines of the plurality of transfer gates QT. Each of selection signals &PHgr;
1
to &PHgr;
48
is connected to the gate electrodes of the plurality of transfer gates QT.
Note that an arbitrary one of gate voltage terminals VG
1
to VG
180
serving as scanning-side extending electrodes is selected, and one gate bus line is selected.
While one gate bus line is selected, selection signals are supplied to the selection signal terminals &PHgr;
1
to &PHgr;
48
sequentially. While one selection signal terminal &PHgr;i(i=1, 2, 3, . . . ) is selected, display signals corresponding to 40 columns are supplied to the display signal terminals VD
1
to VD
40
, to write data in capacitors Ci (i=1, 2, 3, . . . ) serving as memory cells.
Furthermore, the liquid crystal cells LC are driven through the driving transfer gates Q. When this operation is performed 48 times, display data is written in all the liquid crystal cells LC forming a 1-line display portion.
According to the technique shown in Japanese Unexamined Patent Publication No. 4-269791, cost reduction is realized by decreasing the number of drivers on the drain bus lines without increasing the number of drivers on the gate bus lines.
In Japanese Unexamined Patent Publication Nos. 3-38689 and 6-148680 described above, although the number of drain bus drivers is decreased, the number of gate drivers is increased. Hence, further improvements are needed to achieve cost reduction of the liquid crystal display device.
According to Japanese Unexamined Patent Publication No. 4-269791, the ON resistances of transfer gates Q and QT and the capacitances of capacitors CL serving as memory cells in one liquid crystal panel vary due to the manufacturing process. Then, variations occur in the image signal voltage, leading to non-uniform brightness. Times held by the capacitors CL connected to the selection signal terminals and serving as the memory cells differ, possibly causing non-uniform brightness.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation of the prior art, and has as its object to provide an active matrix liquid crystal display device which can improve the brightness uniformity without causing an increase in cost when manufacturing the device, a method of manufacturing the same, and a method of driving the same.
In order to achieve the above object, according to the first main aspect of the present invention, there is provided an active matrix liquid crystal display device comprising: a pair of substrates that seal a liquid crystal; thin film transistors arranged on one of the substrates to form a matrix of n rows×m columns; display pixel electrodes connected to source electrodes of the thin film transistors in one-to-one correspondence; m/s (s and m are natural numbers that render m/s a natural number) drain bus lines connected to drain electrodes of the matrix-type thin film transistors in s-to-1 correspondence; s×n gate bus lines connected to gate electrodes of the thin film transistors on each row in one-to-one correspondence; and a controller for selecting n gate bus lines in each of s frames starting from an (s×t(t is an arbitrary positive integer)+1)th frame and ended with an (s×t+s)th frame, to perform one-screen display with the s frames.
According to the first main aspect described above, gate selection TFTs having drain electrodes, source electrodes, and gate electrodes can be provided, the drain electrodes in units of gate bus lines being connected to gate terminals, the source electrodes being connected to the gate bus lines, and the gate electrodes being connected to gate switch lines that are set at an ON voltage in one frame every s frames.
The gate selection TFTs can be formed simultaneously with the thin film transistors connected to the
Watanabe Makoto
Watanabe Takahiko
Choate Hall & Stewart
Kovalick Vincent E.
Mengistu Amare
NEC Corporation
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