Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2000-06-27
2003-06-17
Kim, Robert H. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S111000, C349S149000, C349S151000
Reexamination Certificate
active
06580486
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix liquid crystal display device, and more particularly to a wiring structure of the active matrix liquid crystal display device.
This specification is based on Japanese Patent Application (Application No. Hei 11-189720), the content of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 12
shows an example of the circuitry for a conventional active matrix liquid crystal display device. In the drawing, the active matrix liquid crystal display device includes pixels disposed at respective intersections between data lines K
1
to Kn and gate lines G
1
to Gm, which are respectively arranged longitudinally and latitudinally, a data driver circuit
200
provided to drive the data lines, and a gate driver circuit
202
provided to drive the gate lines. For each pixel, e.g., pixel
210
formed at the intersection between the gate line Gi and the data line Kj, the pixel is composed of a pixel transistor
212
having a gate connected to the gate line Gi and a source connected to the data line Kj, and liquid crystal capacitance
214
and storage capacitance
216
, which are interconnected through the pixel transistor
212
.
In the active matrix liquid crystal display device shown in
FIG. 12
, a polysilicon thin-film transistor is used for the pixel transistor, and the data driver circuit
200
and the gate driver circuit
202
are integrally formed on the same glass substrate as that of the pixel matrix. The data driver circuit
200
is composed of a scanning circuit
222
and an analog switch array
224
.
In the foregoing active matrix liquid crystal display device including the driver circuits incorporated therein, a block at a time addressing system is typically used in order to simplify the configuration of the data driver circuit. As shown in
FIG. 12
, this driving system is a data line driving system adapted to divide data lines into unit blocks, each block being composed of a plurality of lines (4 lines in the shown example); spread video signals in parallel with the data lines of each block; the number of video signal lines being equal to the number of data lines in each block; and then supply the video signals to the data lines through video signal wiring.
In
FIG. 12
, for example, the blocks are formed such that data lines K
1
to K
4
constitute a block
1
, data lines K
5
to KS constitute a block
2
, and so on. The data lines K
1
to K
4
and the data lines K
5
to K
8
are connected to video signal lines BL
1
to BL
4
, to which video signals are supplied, respectively through the switch transistors Q
1
to Q
4
and the switch transistors Q
5
to Q
8
of the analog switch array
224
. The same applies to the other blocks. In each block, for all the switch transistors of the analog switch array
224
, to which each data line is connected, gates are connected in common, and each gate is connected to one output terminal SPi (i=1 to k) of the scanning circuit
222
.
Now, a description will be made of an operation during the block-at-a-time addressing of the active matrix liquid crystal display device constructed in the foregoing manner by referring to a timing chart of FIG.
13
. It is assumed that the period for supplying video signals equivalent to one line to be displayed by the liquid crystal display device to data lines K
1
to Kn is one horizontal scanning period TH. In one horizontal scanning period TH, the scanning circuit
222
in the data driver circuit
200
sequentially outputs scanning pulses from the output terminals SPi to SPk in synchronization with clock signals DCLK
1
and DCLK
2
used to control the scanning circuit
222
. By these scanning pulses, the switch transistors of the analog switch array
224
are respectively switched ON/OFF by block units.
Then, video signals Vsig equal in number to that of data lines (4 lines in the example of
FIG. 12
) in one, block are spread in parallel, and input from in-put terminals V
1
to V
4
. Then, the switch transistors of the analog switch array
224
are respectively switched ON/OFF by block units, and thus the video signals are input to the data lines by block units. Such an operation is performed for all the blocks and, in one horizontal scanning period TH, a gate line Gx (x=1 to m) having the gate driver circuit
202
located thereon is driven to a voltage (high level in the example shown in
FIG. 12
) for switching ON the pixel transistor. As a result, the video signals equivalent to one line are written in the pixels. Further, by performing such an operation sequentially for all the gate lines, two dimensional videos can be displayed on the liquid crystal display device. In
FIG. 13
, a signal DST denotes a reference signal for defining one horizontal scanning period.
FIG. 14
shows a configuration of a conventional example of an active matrix liquid crystal display device, which includes a precharge circuit
204
provided in a side opposite to the data driver circuit
200
, sandwiching a pixel matrix to reset the data lines K
1
to Kn before the video signals are written therein in FIG.
12
. The precharge circuit
204
is composed of switch transistors N
1
to Nn having sources connected to the end portions of the data lines K
1
to En and gates connected in common. The drains of the switch transistors N
1
to Nn are connected in common, and a precharge signal PCG is input to each gate.
The active matrix liquid crystal display device shown in
FIG. 14
is different in operation from the active matrix liquid crystal display device of
FIG. 12
in the following respects. The output of the gate driver circuit
202
is made during a horizontal blanking period as a period of outputting no video signals, which is included in one horizontal scanning period. During the horizontal blanking period, the device operates to return the output to a potential for switching OFF all the pixel transistors. While the pixel transistors are in OFF states, precharge signals PCG are applied to the switch transistors N
1
to Nn to simultaneously switch ON the switch transistors N
1
to Nn constituting the precharge circuit
204
. All the data lines K
1
to Kn are charged to specified potentials. Other operations are the same as those of the active matrix liquid crystal display device shown in
FIG. 12
, and thus description thereof will be omitted to prevent repetition.
As described above, block-at-a-time addressing is performed in the conventional active matrix liquid crystal display device. However, in such block-at-a-time addressing, in the block boundary-portion of the adjacent data lines of the liquid crystal matrix, a luminance change occurs because of noise (block noise) generated during switching in the analog switching array of the data driver circuit, which results in the appearance of uneven lines.
To exemplify the above problem, reference is made again to FIG.
12
. Through the data lines of the first block, video signals are written in the pixels connected to the respective data lines and, at a next timing, the video signals are written in the respective pixels connected to the data lines, which belong to the second block adjacent to the first block. During the writing of the video signals in the respective pixels connected to the data lines of the second block, the switch transistors Q
1
to Q
4
, constituting the analog switch connected to the data lines of the first block, are in OFF states, and the data lines K
1
to K
4
, belonging to the first block, are in floating states for potentials.
When the switch transistors Q
5
to Q
8
connected to the data lines of the second block are switched ON and, through the data lines K
5
to K
8
of the second block, the video signals are written in the pixels connected to the data lines K
5
to K
8
, fluctuation occurs in the potentials of the data lines K
5
to K
8
. Following the potential fluctuation, the data lines K
1
to K
4
of the first block are also subjected to potential fluctuation because of spatial capacitive coupl
Hayes & Soloway P.C.
Kim Robert H.
NEC Corporation
Schechter Andrew
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