Active matrix liquid crystal display and manufacturing...

Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal

Reexamination Certificate

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Details

C349S039000, C349S147000, C349S149000, C349S139000, C438S030000

Reexamination Certificate

active

06621537

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an active matrix type liquid crystal display apparatus (TFT-LCD) employing thin film transistors (TFTs) as switching elements. More particularly, the present invention has been made for the sake of preventing corrosion of an storage capacitance wiring group during a successive transparent conductive layer etching process in case a metal material of high corrosiveness is employed for the storage capacitance wiring group or collective drawing wiring.
Electrooptical elements employing liquid crystal are actively being applied for use in displays. Electrooptical elements employing liquid crystal are generally arranged in that liquid crystal is interposed between two upper and lower substrates comprised with electrodes which are further interposed by upper and lower polarizing plates, and in case the electrooptical elements are of transmitting type, a back light is additionally arranged in the rear. So-called alignment is performed for the surfaces of the upper and lower electrode substrates, and directors that are average directions of the liquid crystal molecules can be controlled to provide desired initial conditions. Since liquid crystal presents birefringence, light that has been made incident through the polarizing plate from the back light is changed to elliptical polarization through the birefringence and is made incident to the polarizing plate on the opposite side. In case voltage is impressed between the upper and lower electrodes in this condition, the arranging condition of the directors is changed, resulting in a change in the birefringence rate of the liquid crystal layer, in a change in the condition of elliptic polarization made incident to the polarizing plate on the opposite side, and further in a change in the light intensity and spectrum transmitting through the electrooptical elements. While this electrooptical effect is varied by factors such as the type of liquid crystal layer to be employed, initial orientation condition, direction of the polarizing axis of the polarizing plate, thickness of liquid crystal layer or the color filter or various interference filter that are arranged in the path of the transmitting light, these are reported in details in prior art references. Generally, there are employed arrangements known as TN or STN using nematic liquid crystal layers.
Electrooptical elements for displays using liquid crystal may be divided into simple matrix type ones and TFT-LCDs employing TFTs as switching elements. In view of portability and display quality, TFT-LCDs which present superior characteristics than CRTs or simple matrix type liquid crystal display devices are widely applied to note-type personal computers, for example. A TFT-LCD is generally arranged in that liquid crystal is interposed between a TFT array substrate in which TFTs are formed in a form of an array and an opposing substrate formed with a color filter and with common electrodes, this being further interposed between upper and lower polarizing plates, and a back light is further arranged in the rear. Such an arrangement makes it possible to present favorable color displaying characteristics.
For applying voltage on liquid crystal in a TFT-LCD, the TFTs are switched ON within a selected time for the gate lines, charge is applied to pixel electrodes from a source wiring, and the potential of the pixels are made to be identical with those of the source wiring. In case the gates are in a non-selected condition thereafter, the TFTs are set into an OFF condition. While the charge of the pixels is maintained in this condition, the electric charge of the pixels is actually decreased owing to leakage current of the TFTs or within the liquid crystal so that the potential of the pixels is consequently decreased. In order to prevent such variations in the pixel potential, it is general that an storage capacitance is provided so that the amount of variation in the pixel potential with respect to variations in the unit electric charge is kept small. The storage capacitance may be roughly divided into those arranged by gates and pixel electrodes (additional capacity type) and those arranged by an exclusive wiring and pixel electrodes (storage capacitance wiring type). While an additional capacity type is advantageous in that the aperture ratio can be made large since it is not required for the provision of an exclusive wiring unlike storage capacitance wiring types, the current load becomes large since the gate wiring concurrently serve as an storage capacitance wiring. Since the total sum of wiring resistance and storage capacitance becomes large in a large-sized panel, it is general to employ an storage capacitance wiring for the sake of decreasing the load of the gate wiring. A conceptual diagram of a TFT array substrate employing an storage capacitance wiring is shown in FIG.
10
. In the drawing, 1 denotes gate wiring, 8 source wiring, 3 storage capacitance wiring,
10
a
and
10
b
collective drawing wiring for impressing voltage on the storage capacitance wiring. On the other hand, it is being attempted to employ wiring materials of low resistance for the sake of decreasing the wiring resistance. In case of employing Al or Al alloys such as AlSiCu or AlCu for the gate wiring in reversed stagger type TFTs and storage capacitance wiring, it may be that hillocks are generated at the time of forming an insulating film on the wiring pattern or that this insulating film is corroded in a succeeding process by the use of strong acid employed at the time of performing pixel pattern etching. In order to eliminate such troubles, it has been attempted in prior art to prevent hillocks by covering the wiring of Al or one of the above noted Al alloys by a metal pattern of high melting point such as Cr or Mo or to prevent hillocks or corrosion through strong acid by performing anodic oxidation of Al or Al alloys. However, the increase in number of photolithographic processes to be performed or the additional step of performing anodic oxidation results in inferior productivity. On the other hand, it has also been attempted to employ Al alloys such as AlZr or AlTa for preventing hillocks, but this resulted in a drawback in that the resistivity was increased to be substantially identical with those of metals of high melting points such as Cr. It has recently been developed of a wiring material as disclosed in Japanese Patent No. 2733006 wherein it is mentioned that with AlNd, hillocks can be prevented without being accompanied by increases in resistivity unlike AlZr as described earlier. It will now been explained for a method of manufacturing a TFT array substrate as shown in FIG.
8
and
FIG. 9
which has been manufactured through conventional methods by using AlNd for the gate wiring and storage capacitance wiring.
After forming AlNd onto a glass substrate through spattering to a thickness of 200 nm, wet etching is performed by using a mixed liquid of phosphoric acid, acetic acid and nitric acid to form gate wiring
1
, storage capacitance electrodes
2
and storage capacitance wiring
3
. At this time, the storage capacitance wiring was connected to a collective drawing wiring
3
a
on the reverse side of gate terminals. Then, there are successively formed, through plasma CVD, SiN to a thickness of 400 nm as a gate insulating film
4
, amorphous Si of 150 nm as a semiconductor layer, and a P doped amorphous Si impurity layer of 30 nm, and a semiconductor pattern
5
is formed on the gate wiring by patterning the impurity layer and semiconductor layer. Thereafter, pixel electrodes
6
are obtained by forming a pixel electrode film to a thickness of 100 nm, which is patterned by a mixed acid of hydrochloric acid and nitric acid or the like. Contact holes
7
a
are formed through the gate insulating film at an end of the storage capacitance wiring on the side of the gate terminal. After successively forming Cr to a thickness of 400 nm for forming source wiring
8
and drain electrodes
9
, patterning is performed. Th

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