Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-09-23
2002-07-16
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C087S026000, C087S026000, C087S026000
Reexamination Certificate
active
06421038
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an active matrix liquid crystal display, and more particularly, to an active matrix liquid crystal display, wherein it is provided with a device for applying a gate pulse to transistors connected to picture elements (or pixels) consisting of a liquid crystal.
2. Description of the Related Art
The conventional active matrix liquid crystal display apparatus displays a picture by controlling the light transmissivity of liquid crystal using an electric field. As shown in
FIG. 1
, such a liquid crystal display apparatus includes a data driver
12
for driving signal lines SL
1
to SLm at a liquid crystal panel
10
, and a gate driver
14
for driving gate lines GL
1
to GLn at a liquid crystal panel
10
. In the liquid crystal panel
10
, pixels
11
connected to signal lines SL and gate lines GL are arranged in an active matrix pattern. Each pixel
11
includes a liquid crystal cell C
1
c for responding to a data voltage signal DVS from the signal line SL to control a transmitted light quantity, and a thin film transistor (TFT) CMN for responding to a scanning signal SCS from the gate line GL to switch the data voltage signal DVS to be applied from the signal line SL to the liquid crystal cell C
1
c. As the gate lines GL
1
to GLn are sequentially driven, the data driver
12
applies the data voltage signal DVS to all the signal lines SL
1
to SLm. The gate driver
14
allows the gate lines GL
1
to GLn to be sequentially enabled for each horizontal synchronous interval by applying the scanning signal SCS to the gate lines GL
1
to GLn sequentially. To this end, the gate driver
14
consists of a shift register
16
responding to a gate start pulse GSP from a control line CL and a gate scanning clock GSC from a gate clock line GCL, and a level shifter
18
connected between the shift register
16
and the gate lines GL
1
to GLn. The shift register
16
outputs the gate start pulse GSC from the control line CL to any one of n output terminals QT
1
to QTn and, at the same time, responds to the gate scanning clock GSC to shift the gate start pulse GSP from the first output terminal QT
1
to the nth output terminal QTn sequentially. The level shifter
18
generates n scanning signals SCS by shifting voltage levels of the output signals of the shift register
16
. To this end, the level shifter
18
consists of n inverters
19
that are connected between the n output terminal QT
1
to QTn the shift register
16
and the n gate lines GL
1
to GLn, respectively, and fed with low and high level gate voltages Vgl and Vgh in a direct current shape from a first and a second voltage line FVL and SVL, respectively. The inverters
19
selectively supply any one of the low and high level gate voltages Vg
1
and Vgh to the gate line GL in accordance with a logical state at the output terminal QT of the shift register
16
. Accordingly, only one of the n scanning signals SCS has the high level gate voltage Vgh.
In this case, the TFT CMN receiving a scanning signal SCS having the high level gate voltage Vgh from the gate line GL is turned on, and the liquid crystal cell C
1
c charges the data voltage signal DVS during an interval when the TFT CMN is turned on. The voltage charged into the liquid crystal cell C
1
c in this manner drops down when the TFT CMN is turned off and therefore becomes lower than a voltage of the data voltage signal DVS. Accordingly, a feed through voltage Vp corresponding to a difference of voltage between the voltage charged in the liquid crystal cell and the data voltage signal DVS, is generated. This feed through voltage )Vp is caused by a parasitic capacitance existing between the gate terminal of the TFT CMN and the liquid crystal cell C
1
c, which changes a transmitted light quantity at the liquid crystal cell C
1
c periodically. As a result, a flicker and a residual image are generated at a picture displayed on the liquid crystal panel.
In order to suppress such a feed through voltage )Vp, as shown in
FIG. 1
, support capacitors Cst are connected, in parallel, to the liquid crystal cells. The support capacitor Cst compensates for the liquid crystal cell voltage when the TFT CMN is turned off, thereby suppressing the feed through voltage )Vp as expressed in the following formula:
Vp=
(
V
on−
V
off)·
Cgs/C
1
c+Cst+Cgs
(1)
in which Von represents a voltage at the gate line GL upon turning on of the TFT CMS; Voff represents a voltage at the gate line GL upon turning off of the TFT CMS; and Cgs represents a capacitance value of a parasitic capacitor existing between the gate terminal of the TFT CMN and the liquid crystal cell. As seen from formula (1), the feed through voltage )Vp increases depending on a voltage difference at the gate line GL upon turning on and turning off of the TFT CMN.
In order to sufficiently suppress the feed through voltage )Vp, a capacitance value of the support capacitor Cst must be increased. This causes aperture ratio of display area to be decreased, so that it is impossible to obtain a sufficient display contrast. As a result, it is difficult to suppress the feed through voltage )Vp sufficiently by means of the support capacitor Cst.
As another alternative for suppressing the feed through voltage )Vp, there has been suggested a liquid crystal display apparatus adopting a scanning signal control system for allowing the falling edge of the scanning signal SCS to have a gentle slope. In the liquid crystal display apparatus of a scanning signal control system, the falling edge of the scanning signal SCS changes in the shape of a linear function as shown in
FIG. 2A
, an exponential function as shown in
FIG. 2B
, or a ramp function as shown in FIG.
2
C. Examples of such a liquid crystal display apparatus of scanning signal control system are disclosed in the Japanese Patent Laid-Open Gazette Nos. 1994-110035 and 1997-258174 and the U.S. Pat. No. 5,587,722. However, these liquid crystal display devices of a scanning signal control system additionally require a circuit modification of the gate driver or a new waveform modifying circuit to be positioned between the gate driver and each gate line at the liquid crystal panel. The gate driver described in the U.S. Pat. No. 5,587,722 has a complex circuitry and consumes a great amount of power, because a circuit allowing the falling edge of the scanning signal to be stepwise is formed in a gate driver chip.
For example, as shown in
FIG. 3
, the liquid crystal display apparatus of a scanning signal control system disclosed in the Japanese Patent Laid-Open Gazette No. 1994-110035 includes an integrator
22
connected between a scanning driver cell
20
and a gate line GL. The integrator
22
consists of a resistor R
1
between the scanning driver cell
20
and the gate line GL, and a capacitor C
1
connected between the gate line GL and the ground voltage line GVL. The integrator
22
integrates a scanning signal SCS to be applied from the gate driver cell
20
to the gate line GL, thereby changing the falling edge of the scanning signal SCS into a shape of exponential function. A TFT CMN included in a pixel
11
is turned on until a voltage of the scanning signal SCS from the gate line GL drops less than its threshold voltage. At this time, an electric charge charged in a liquid crystal cell C
1
c is pumped into the gate line GL through Cgs. However, sufficient electric charge is charged into the liquid crystal cell C
1
c by means of a data voltage signal DVS passing through the TFT CMN from a signal line SL. As a result, the voltage charged in the liquid crystal cell C
1
c does not drop. Then, since a voltage variation amount in the gate line GL is a maximum threshold voltage of the TFT CMN when a voltage of the scanning signal SGS at the gate line GL drops less than a threshold voltage of the TFT CMN, electric charge amount pumped from the liquid crystal cell C
1
c into the gate line GL becomes very small. As a result, the feed through voltage )Vp can be suppressed sufficientl
Dinh Duc Q.
Hjerpe Richard
LG. Philips Lcd Co., Ltd.
Long Aldridge & Norman LLP
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