Active matrix drive circuits

Details Active matrix drive circuits Active matrix drive circuits

1998-04-03

2001-05-15

Saras, Steven (Department: 2675)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S100000

Reexamination Certificate

active

06232946

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to active matrix drive circuits and is concerned more particularly, but not exclusively, with drive circuits for active matrix liquid crystal displays (AMLCD'S).
The invention can be applied, for example, to drive circuits for driving matrix-addressed grey-scale thin-film display panels, such as AMLCD'S, with digital data, and can be implemented in a compact and area efficient manner. The circuit can be constructed with conventional large scale integration (LSI) to form chip-on-glass (COG) data drive circuits, although the circuit offers particularly significant advantages in terms of area efficiency when implemented using thin-film transistors (TFT) integrated on the display substrate.
2. Description of the Related Art
FIG. 1
shows a typical AMLCD
1
composed of N rows and M columns of pixels addressable by scan lines
2
connected to a scan line driver circuit
3
and data lines
4
connected to a data line driver circuit
5
. Data voltages are applied to the data lines
4
by the data line driver circuit
5
and scan voltages are applied to the scan lines
2
by the scan line driver circuit
3
so that such voltages in combination serve to apply analogue data voltages to the pixel electrodes
6
(as best seen in the enlarged detail of the display in the lower half of the figure) in order to control the optical transmission states of the pixels along each row as the rows are scanned in a cyclically repeating sequence. This is achieved as follows for a single row of pixels. The data line driver circuit
5
reads serial analogue or digital data to be displayed by the row of pixels, and applies parallel analogue data voltages to the data lines
4
so as to charge up each data line
4
to the required data voltage. The scan line
2
corresponding to the row of pixels to be controlled is activated by the application of the scan voltage by the scan line driver circuit
3
so that a TFT
7
associated with each pixel is switched on to transfer charge from the corresponding data line
4
to a pixel storage capacitance
8
(as shown in broken lines in the figure) associated with the pixel. When the scan voltage is removed the TFT
7
isolates the pixel storage capacitance
8
from the data line
4
so that the optical transmission state of the pixel corresponds to the voltage across the pixel storage capacitance
8
until the pixel is refreshed during the next scanning frame. The rows of pixels are refreshed one at a time until all the rows have been refreshed to complete refreshing of a frame of display data. The process is then repeated for the next frame of data.
The data line driver circuit
5
for such a display can be implemented using conventional LSI and bonded to the periphery of the display using COG techniques, or alternatively the circuit can be fabricated monolithically on the display substrate using polysilicon TFT circuitry. However, since the data line driver circuit
5
of such a display requires more sophisticated circuitry than the scan line driver circuit
3
, it will be apparent that it is the form of circuit used for the data line drive which will have the more significant impact on the viability of implementing the drive electronics using monolithic low performance TFT circuitry.
The most straightforward driving scheme for such a display is the point-at-a-time driving scheme, and
FIG. 2
shows an analogue data line driver circuit
10
which may be employed in such a driving scheme. In this circuit
10
a shift register composed of a chain of D-type flip-flops
11
is connected so that the output of each flip-flop
11
controls the gate of an associated sampling transistor
12
for sampling the analogue video input signal AVIDEO and for applying the sampled signal to the corresponding data line
4
with its associated parasitic capacitance, shown in broken lines at
13
in the figure. For a colour display there are three analogue video lines, one for each RGB signal. In operation frame and line synchronisation pulses VSYNC and HSYNC indicate the start of a frame period and a line period respectively, and a clock signal CK at the sampling frequency is applied to the clock inputs of the flip-flops
11
so that a circulating “
1
” state within the shift register sequentially activates the sampling transistors
12
at the sampling frequency. The RC time constant formed by the on resistance of the sampling transistor
12
and the resistance and distributed capacitance of the data line
4
must be sufficiently less than the available sampling period (1/fNM) for the sampling to be executed successfully.
FIG. 4
a
is a timing diagram showing the timing of the signals associated with such a point-at-a-time data line driver circuit
10
, where S
1
, S
2
and S
3
refer to the scan voltages applied to the first three scan lines numbered from the top of the display. It will be noted that the AVIDEO signal is sampled at the same time as application of the data voltages to the pixels on activation of the scan lines in successive scanning line periods T
1
, T
2
. . . by the scan voltages S
1
, S
2
, S
3
, such scan voltages being synchronised by the HSYNC pulses. In order to increase the length of the sampling window, it is possible to use multiple phase timing registers which sample a multiphase analogue input signal. However a realistic limit of four phases restricts the point-at-a-time driving scheme to relatively small displays having low capacitance data lines, or alternatively low resolution displays having a slow data rate.
For analogue displays of large size or high, pixel resolution, in which the RC time constant of the data lines is larger than the available sampling window for the point-at-a-time driving scheme, it is necessary for a line-at-a-time driving scheme to be used instead, and
FIG. 3
a
shows an analogue data line driver circuit
20
which may be employed in such a driving scheme. In this circuit
20
a shift register composed of a chain of D-type flip-flops
21
is connected so that the output of each flip-flop
21
controls an associated sampling circuit
22
for sampling the AVIDEO signal and applying the sampled signal to the corresponding data line
4
with its associated parasitic capacitance, shown in broken lines at
23
in the figure. As shown in the enlarged detail of
FIG. 3
b,
each of the sampling circuits
22
supplied with control signals by a control circuit
24
comprises two control gates
25
and
26
, two small storage capacitors
27
and
28
, and a buffer
29
. In each case the capacitor
27
or
28
is employed to store a sample of the AVIDEO signal, and the voltage on each capacitor is then transferred to the data line by the buffer
29
. Two storage capacitors
27
and
28
are normally sued since the sampling of the serial input data and the driving of the data lines cannot take place simultaneously. While the capacitor
27
is being used for sampling, the capacitor
28
and the buffer
29
are driving the data line. During the next line period, the capacitor
27
and buffer
29
are used to drive the data line, whilst the capacitor
28
is used for the next line sample. Thus, at any one instant, a whole line of video data is stored in the analogue memory consisting of the capacitors
27
and
28
.
FIG. 4
b
is a timing diagram showing the timing of the signals associated with such a line-at-a-time data line driver circuit
20
, for comparison with the point-at-a-time timing diagram of
FIG. 4
a.
the important feature of the line-at-a-time driving scheme is that the scan line is activated only after a complete line of data has been sampled during line period T
1
, the next complete line period T
2
being used for scanning of the data to the pixels as well as sampling of the data for the row of pixels (as opposed to the point-at-a-time driving scheme of
FIG. 4
a
where sampling and scanning occur in each of the line periods T
1
and T
2
). However the implementation of the line memory and buffering incurs a significant overhead both in te

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