Active matrix drive circuit

Details Active matrix drive circuit Active matrix drive circuit

1998-04-03

2001-07-24

Saras, Steven (Department: 2675)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S098000

Reexamination Certificate

active

06266041

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to drive circuits for active matrix devices and is concerned more particularly, but not exclusively, with drive circuits for active matrix liquid crystal displays (AMLCD's).
The drive circuits of the invention can be used to generate the control and data signals for thin-film display panels and two-dimensional imaging equipment, for example, and find particular application in computer graphics displays receiving digital RGB data. In such displays, digital data driver circuits are provided which may be implemented in separate large scale integration (LSI) driver chips mounted on the display panel, or which may alternatively be integrated on the display panel in the form of thin-film transistors (TFT) using silicon-on-insulator (SOI) technology, and preferably the emerging polysilicon technology. In either of these two alternative implementations, the digital data line driver circuits must be adapted to convert the data input in the form of parallel digital data into analogue voltages to be applied to the pixels of the display by means of digital-to-analogue (D/A) converters. Although the construction of the D/A converters used may vary, most D/A converters require more than one (pixel frequency) control signal for successful operation, and the driver circuits of the invention are particularly advantageous in such circumstances.
DESCRIPTION OF THE RELATED ART
FIG. 1
a
shows a typical AMLCD
1
composed of N rows and M columns of pixels addressable by scan lines
2
connected to a scan line driver circuit
3
and data lines
4
connected to a data line driver circuit
5
. Data voltages are applied to the data lines
4
by the data line driver circuit
5
and scan voltages are applied to the scan lines
2
by the scan line driver circuit
3
so that such voltages in combination serve to apply analogue data voltages to the pixel electrodes
6
(as best seen in the enlarged detail of a part of the display shown in
FIG. 1
b
) in order to control the optical transmission states of the pixels along each row as the rows are scanned in a cyclically repeating sequence. This is achieved as follows for a single row of pixels. The data line driver circuit
5
reads a line of data to be displayed by the row of pixels and applies corresponding data voltages to the data lines
4
so as to charge up each data line
4
to the required data voltage. The scan line
2
corresponding to the row of pixels to be controlled is activated by the application of the scan voltage by the scan line driver circuit
3
so that a TFT
7
associated with each pixel is switched on to transfer charge from the corresponding data line
4
to a pixel storage capacitance
8
(as shown in broken lines in the figure) associated with the pixel. When the scan voltage is removed the TFT
7
isolates the pixel storage capacitance
8
from the data line
4
so that the optical transmission state of the pixel corresponds to the voltage across the pixel storage capacitance
8
until the pixel is refreshed during the next scanning frame. The rows of pixels are refreshed one at a time until all the rows have been refreshed to complete refreshing of a frame of display data. The process is then repeated for the next frame of data.
It is known, for example from European Published Patent Application No. 0678845, to form the data line driver circuit
5
from a shift register
9
and a bank
10
of data line drivers (one driver per column of pixels). Furthermore the scan line driver circuit
3
typically consists of a shift register
14
and a bank
15
of scan line buffers (one buffer per row of pixels). Furthermore it is known, for example from U.S. Pat. No. 4,612,659, to form the data line driver circuit
5
from a shift register
9
composed of a cascaded chain of D-type flip-flops (DFF's) and a bank
10
of data line drivers in the form of TFT's
12
for sampling an analogue video (AVIDEO) signal and charging the corresponding data lines
4
having associated parasitic capacitances
13
as shown in broken lines in the small figure. In operation the shift register
9
is initialised by a horizontal synchronisation signal HSYNC such that the outputs of all but one of the DFF's
11
are set at a low logic level ‘0’ and the output of the remaining DFF
11
is set at a high logic level ‘1’. The shift register
9
is then clocked by a clock signal CK at the pixel data rate frequency which is equal to small f×N×M Hz, where f is the frame rate of the display. This causes the DFF
11
having its output at level ‘1’ and the following DFF
11
having its output at level ‘0’ to change state, so that the level ‘1’ effectively circulates within the shift register
9
at the clocking frequency, and as a result sequential pulses are generated for application to the data lines
4
. Such a point-at-a-time driving scheme is widely used for analogue displays of small size or low pixel resolution.
Several improvements to such a driving scheme have been proposed. U.S. Pat. No. 4,785,297 discloses a data line driver circuit having a shift register consisting of a chain of master-slave flip-flops with both the master output and the slave output of each flip-flop being used to control the data line drivers, thus enabling the clocking rate of the shift register to be reduced. It is now common practice for the shift register of such a data line driver circuit to be composed of a chain of latches. Also, in order to minimise both the capacitative loading of the clock line or lines and the power consumption of the circuit, it is known to apply state-controlled clocking schemes to the shift register. For example U.S. Pat. No. 4,746,915 discloses a data line driver circuit comprising a first shift register which is split into smaller banks of DFF's or latches and a further shift register, operating at a lower frequency than the first shift register, which is used to selectively apply a clock signal to each bank of DFF's or latches. However, in all these circuit arrangements, it is only the flip-flop having its output at the ‘1’ level and the flip-flop having a ‘1’ at its input which require clocking in response to each clock pulse.
FIG. 3
shows a data line driver circuit
20
in which the input and output of each DFF
21
is coupled to a respective input of an associated OR gate
22
which controls a pass gate
23
so as to ensure that only the required DFF's
21
are clocked by each clock pulse, as disclosed by T. Maekawa, Y. Nakayama, Y. Nakajima, M. Ino, H. Kaneko, M. Satoh and M. Kobayashi, ‘A 1.35-in.-diagonal wide-aspect-ratio poly-Si TFT LCD with 513 k pixels’, Journal, Pages 414-417, 1994.
The complexity of the data line drivers of such data line driver circuits is dependent on the size and resolution of the display and whether the display interface is analogue or digital. As already mentioned, the very simple data line drivers of the point-at-a-time driving scheme of
FIG. 2
are adequate for analogue displays of small size or low pixel resolution. However, for a line-at-a-time driving scheme, such as that of A. Lewis and W. Turner, ‘Driver circuits for AMLCD's’, Journal of the Society for Information Display, Pages 56-64, 1995, more complex data line drivers are required, and this necessitates an increased number of control signals for controlling the operation of the circuit. For a typical analogue line-at-a-time data line driver circuit, each data line driver comprises two capacitative memory elements for storing sample signals and two data line buffers for applying the stored sample signals to the data lines, and, in addition to the pixel data rate sampling pulse, control signals are needed to select which of the two capacitative memory elements is used and which of the two data line buffers is enabled. These control signals generally operate at the line frequency of the display.
FIG. 4
shows the general architecture of a digital line-at-a-time data line driver circuit
30
which comprises an input register
31
to which digital video dat

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