Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1997-02-26
2001-08-28
Jankus, Almis R. (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S092000, C345S099000, C345S212000, C345S213000
Reexamination Certificate
active
06281870
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix display device in which pixels arranged in a matrix and driving circuits disposed peripheral thereto are formed so as to be incorporated, and in particular to the structure of such a peripheral circuit.
2. Description of the Related Art
By referring to
FIG. 6
, an example of a conventional active matrix display device will be briefly described.
The display device has pixels LC arranged in a matrix as shown in the figure. The respective pixels include pixel electrodes formed on one substrate and counter electrodes formed on another substrate, with an electro-optical material such as liquid crystal provided therebetween. A predetermined voltage V
com
is applied to the counter electrodes. The respective pixels LC are connected in parallel to additional capacitors Cs. In addition, thin film transistors Tr are formed so as to be integrated, as switching devices for driving the respective pixels LC. Gate lines X are arranged along the row direction of the pixels LC arranged in a matrix, while data lines Y are arranged along the column direction perpendicular thereto. The source electrodes of the thin film transistors are connected to the corresponding data lines Y, while the gate electrodes are connected to the corresponding gate lines X.
The display device further includes a vertical driving circuit
101
and a horizontal driving circuit
102
. The vertical driving circuit
101
sequentially outputs selection pulses to the gate lines X, enabling the thin film transistors Tr on the same gate line to be conductive, and performs line-sequential-scanning of the pixels LC in line units. The vertical driving circuit
101
sequentially transfers a vertical start signal VST that is inputted from an external timing generator, in synchronism with a vertical clock signal VCK which is similarly inputted from the timing generator, and thereby outputs the above-mentioned selection pulses. Also, the horizontal driving circuit
102
controls switching of switches HSW connected to the respective data lines Y. The data line Y are supplied with a video signal SIG that is separated into three primary color components of red, green and blue. In synchronism with a horizontal clock signal HCK inputted from the external timing generator, the horizontal driving circuit
102
outputs selection pulses, which control switching of the switches HSW, by sequentially transferring a horizontal start signal HST similarly inputted from the timing generator in one horizontal period. Thereby, the video signal is written into the pixels LC in the row selected in each horizontal period.
FIG. 7
shows a block diagram of an example of the detailed structure of the horizontal driving circuit
102
. The vertical driving circuit
101
also has a similar structure. The horizontal driving circuit
102
outputs the selection pulses &phgr; for sequentially switching the switches HSW shown in FIG.
6
. The horizontal driving circuit
102
consists of D-type flip-flops (D-F/F) connected in series in multistages which correspond to the number of the pixel columns. When receiving the clock signal HCK, the horizontal driving circuit
102
sequentially transfers the start signals HST, and thereby outputs the selection pulses &phgr;.
Also in active matrix display devices having a screen consisting of matrix-arranged pixels and peripheral driving circuits, the screen has been being developed for larger size and higher resolution. This case increases the number of connected D-F/F which are included in a shift register which constitutes a driving circuit. As shown in
FIG. 7
, if a defect occurs in part of the D-F/Fs connected in series or at a connection, the horizontal start signal HST is not transferred after where the defect occurs, and selection pulses are not outputted in the remaining stages. Consequently, video signals cannot be written into the portions of the screen corresponding to the remaining stages, which thus causes a fatal inferior display. In addition, according to the conventional driving circuit using the shift register, the sequence of the selection pulses outputted becomes uniform, which makes it difficult to perform various displays with respect to the screen.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an active matrix display device in which pixels arranged in a matrix and driving circuits disposed peripheral thereto are formed so as to be incorporated.
According to the present invention, the foregoing object is achieved through the provision of an active matrix display device including: a plurality of gate lines and a plurality of data lines formed on a substrate so as to be mutually perpendicular; pixels arranged at the intersections of the gate lines and the data lines, the pixels being driven via the gate lines and the data lines; a first driving circuit formed on the substrate, for outputting selection pulses selecting each gate line; and a second driving circuit formed on the substrate, for outputting selection pulses selecting each data line, the first driving circuit and/or the second driving circuit including an address counter for counting the number of clock signals inputted from the exterior and sequentially outputting an address signal, and a plurality of address decoders for decoding the address signal and sequentially outputting selection pulses.
Preferably, the address counter supplies the address signal as parallel bit data to address lines, and each address decoder connected in common to the address lines decodes the parallel bit data and outputs selection pulses when an address signal assigned to each address decoder is inputted.
The address counter may supply the address signal with it separated into an upper address signal and a lower address signal, and the active matrix display device may include selectors for selecting the plurality of address decoders together in block units and a block decoder for sequentially specifying each block unit.
Preferably, the block decoder decodes the upper address signal and uses one selector belonging to a specified block unit to select the address decoder belonging to the specified block, and the selected address decoder decodes the lower address signal and sequentially outputs selection pulses.
When the address counter counts the number of the clock signals inputted from the exterior and outputs the address signal, the address counter may be capable of switching between ascending order and descending order.
When the address counter counts the number of the clock signals inputted from the exterior and outputs the address signal, the address counter may be capable of changing the range of counting, and a screen partially appears in accordance with the changed range.
The pixels may be provided by an electro-optical material sandwiched between pixel electrodes formed on the substrate and counter electrodes opposite to the substrate.
The pixels may be driven by first thin film transistors formed on the substrate, and the first driving circuit and the second driving circuit may include second thin film transistors.
As set forth in the foregoing description, according to the present invention, the driving circuit peripherally included in the active matrix display device has the address counter for counting the number of clock signals inputted from the exterior and sequentially outputting the address signal, and a plurality of address decoders for decoding the address signal and sequentially outputting selection pulses. Employment of such an address decoding method makes it possible to avoid a display defect due to inferior transfer by the shift register, which is a conventional problem. In addition, the address decoding method basically enables random access, which readily realizes inverted display on the screen and separated displays on the screen.
REFERENCES:
patent: 4748444 (1988-05-01), Arai
patent: 5028916 (1991-07-01), Ichikawa et al.
patent: 5051739 (1991-09-01), Hayashida et al.
patent: 5151689 (1992-09-
Awad Amr
Jankus Almis R.
Sonnenschein Nath & Rosenthal
Sony Corporation
LandOfFree
Active matrix display device with peripherally-disposed... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Active matrix display device with peripherally-disposed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Active matrix display device with peripherally-disposed... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2531931