Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-10-19
2002-09-10
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S100000, C345S206000
Reexamination Certificate
active
06448954
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix display device and, more specifically, to an active matrix display device incorporating driver circuits.
2. Description of the Related Art
The active matrix display device means a display device in which as shown in
FIG. 20
pixels are arranged at intersections of a matrix and each pixel is provided with a switching element, and pixel information is controlled by on/off switching of the switching element. The active matrix display device uses a liquid crystal
1
as a display medium. In the invention, a thin-film transistor
2
, which is a three-terminal device having the gate, source, and drain, is used as the switching element.
In the matrix, the term “row” means a structure in which a scanning line (gate line)
3
extending parallel with the associated row is connected to the gate electrodes of thin-film transistors
2
of the associated row. The term “column” means a structure in which a signal line (source line)
4
extending parallel with the associated column is connected to the sources (or drains) of thin-film transistors
2
of the associated column. The circuit for driving the scanning lines
3
is called a scanning line driver circuit, and the circuit for driving the signal lines
4
is called a signal line driver circuit. The thin-film transistor is abbreviated as “TFT”.
FIGS. 21A and 21B
show a first example of a conventional active matrix liquid crystal display device. Reference numerals
11
denotes an amorphous TFT active matrix, and numerals
12
and
13
denote single crystal silicon driver circuit ICs.
In this active matrix liquid crystal display device, the TFTs are formed by using amorphous silicon, the scanning line and signal line driver circuits are single crystal silicon integrated circuits and are mounted around a glass substrate by means of tabs (see
FIG. 21A
) or by using a COG (chip on glass) technique (see FIG.
21
B).
This type of liquid crystal display device has the following problems.
First, there is a reliability problem because the signal lines and the scanning lines are connected to the active matrix via tabs or bonding wires. For example, in the case of a VGA (video graphic display) display device, the number of signal lines is 1,920 and the number of scanning lines is 480. These numbers are increasing year by year with the increase in resolution.
Second, in the case of producing a view finder for a video camera or a liquid crystal projector, a compact display device is needed. However, for these purposes, a liquid crystal display device using tabs is disadvantageous in terms of a space occupied by it.
To solve the above problems, an active matrix liquid crystal display device using polysilicon TFTs has been developed.
FIG. 22
shows its example. In this display device, by using polysilicon TFTs, a signal line driver circuit
17
and a scanning line driver circuit
18
are formed on a glass substrate
15
at the same time as pixel TFTs that constitute an active matrix
16
. The polysilicon TFTs are formed either by a high-temperature polysilicon process in which elements are formed on a quartz substrate by a process of higher than 1,000° C., or by a low-temperature process in which elements are formed on a glass substrate by a process of lower than 600° C.
The polysilicon TFT can attain a mobility of larger than 30 cm
2
/V.s and can operate with a signal of about several megahertz in contrast to the fact that the mobility of the amorphous silicon TFT is about 0.5 cm
2
/V.s.
Driver circuits for driving an active matrix liquid crystal display device are classified into a digital type and an analog type. Since the number of elements needed in a digital driver circuit is much larger than in an analog driver circuit, driver circuits using polysilicon TFTs generally employ an analog scheme. Further, each of the scanning line driver circuit and the signal line driver circuit may be configured in two different ways, that is, by using a shift register or a decoder.
A driver circuit using a shift register will be described first.
FIG. 23
is a block diagram of a shift register. In a commonly used configuration of a shift register
20
, a D-type flip-flop (hereinafter abbreviated as “DFF”)
21
is formed by combining clocked inverters and inverters.
FIGS. 24A-24E
show an example of a DFF. Specifically,
FIG. 24A
shows a circuit configuration of a DFF,
FIGS. 24B and 24D
show a circuit configuration of a clocked inverter
25
that is a component of the DFF, and
FIGS. 24C and 24E
show a circuit configuration of an inverter
26
that is another component. There is another type of DFF which uses transmission gates.
Referring to
FIGS. 25A and 25B
, a description will be made of a signal line driver circuit that is formed by combining a shift register, inverter-type buffers, and transmission gates (hereinafter referred to as “TM gates”).
A start pulse (SP) and clocks (CL and /CL) are input to the first stage of a shift register.
FIGS. 25A and 25B
are a block diagram and a timing chart of the signal line driver circuit. In
FIG. 25B
, waveforms at points A-F in
FIG. 25A
are shown and t
1
-t
8
denote time periods.
Each of periods t
1
-t
8
is a half of the clock pulse cycle. The start pulse changes from High to Low in period t
1
. Since a clocked inverter
31
performs an inverter operation, a waveform at point A has a phase opposite to the phase of the start pulse. The phase of a waveform at point B is further reversed.
During period t
2
, the clock inverter
31
is rendered non-operating and a clocked inverter
32
operates as an inverter. As a result, at point A, the final state of period t
1
, i.e., Low, is maintained. At point B, where the phase is opposite to the phase at point A, the final state of period t
1
, i.e., High, is maintained. A clocked inverter
33
operates during period t
2
. As a result, Low, i.e., an opposite phase to the phase at point B, appears at point C, and High, i.e., the same phase as at point B, appears at point D.
Next, during period t
3
, clocked inverters
31
,
34
and
35
operate and clocked inverters
32
,
33
and
36
are rendered non-operating. As a result, Low, which is the same as the sate of the input start pulse, appears at point B, and the final state of period t
2
, i.e., High, is maintained at point D. At point F, where the phase is the same as at point D, High is maintained.
Next, during period t
4
, the clocked inverters
31
,
34
and
35
are rendered non-operating and the clocked inverters
32
,
33
and
36
operate. As a result, Low appears at points B and D, and High appears at point F. The shift register using the DFFs operates in the above manner (see
FIG. 25B
) to transfer signals sequentially. In
FIG. 25A
, reference numerals
37
-
39
denote clocked inverters,
52
denotes a video signal line, and
53
-
55
denote signal lines.
Outputs of the respective stages at points B, D and F are transferred to TM gates
49
-
51
via inverter-type buffers
40
-
48
. Inverter-type buffers are used to drive large-sized transistors of a TM gate, and have a size ratio of about 1:3 in each buffer stage.
When one of the TM gates
49
-
51
is turned on, the video signal line
52
is short-circuited with one of the signal lines
53
-
55
in the matrix and a video signal is written to the signal line. The written signal is held by the signal line until the next writing, because each signal line, the opposed substrate, and the liquid crystal in between constitute a capacitor in the matrix. Where the capacitance is insufficient, a thin-film capacitor is connected to each signal line to hold a signal.
As described above, the maximum operating frequency of a shift register is about several megahertz in the case of a polysilicon TFT driver circuit. However, a signal cannot be used as it is in the case of VGA in which the reference clock frequency is 25 MHz. Even higher frequencies of 50 MHz and 100 MHz are used in XGA and EWS, which are higher level standards than VGA. Naturally the polysilicon TFT dri
Chimura Hidehiko
Katoh Ken-ichi
Koyama Jun
Kubota Yasushi
Chang Kent
Semiconductor Energy Laboratory Co,. Ltd.
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