Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2001-10-19
2004-10-05
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Reexamination Certificate
active
06801194
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a display device, and more particularly, to an active matrix type display device thereof.
In an active matrix type liquid crystal display device, pixel regions are formed on a liquid crystal side surface of one of a pair of substrates, which are arranged so as to face each other in an opposed manner, with a liquid crystal being disposed therebetween. The pixels are formed as regions which are surrounded by gate signal lines that extend in the x direction and are arranged in parallel in the y direction and drain signal lines that extend in the y direction and are arranged in parallel in the x direction.
Each pixel region is provided with a thin film transistor, which is operated upon receiving a scanning signal from one gate signal line, and a pixel electrode to which video signals from the drain signal line are supplied through the thin film transistor.
This pixel electrode generates an electric field between the pixel electrode and a counter electrode which is formed on the other substrate side, for example, and the light transmittivity of the liquid crystal disposed between these electrodes is controlled by this electric field.
Such a liquid crystal display device is provided with a scanning signal driving circuit, which supplies scanning signals to respective gate signal lines and a video signal line driving circuit which supplies video signals to respective drain signal lines.
In view of the fact that the scanning signal driving circuit and the video signal line driving circuit are constituted of a large number of MIS (metal insulator semiconductor) transistors having a constitution similar to that of the thin film transistors formed inside of the pixel regions, a technique has been employed in which semiconductor layers of these respective transistors are formed of polycrystalline silicon (p-Si), and the scanning signal driving circuit and the video signal line driving circuit are formed on a surface of one substrate along with the formation of the pixels.
The scanning signal driving circuit is a circuit which mainly uses a shift register, and the video signal line driving circuit also uses a shift register at a portion thereof. However, there has been a recent demand for a shift register which can be operated at high speed at a low voltage and with a low power and has no through-current. To meet this demand, a shift register which is referred to as dynamic ratio shift register has been proposed, for example.
A dynamic ratio shift register of the type mentioned above has been disclosed in Japanese Patent Publication No. 45638/1987, for example, and the constitution thereof is illustrated in FIG.
9
A. Further,
FIG. 9B
shows a timing chart of the circuit shown in
FIG. 9A
, which timing chart shows respective outputs VN
1
and VN
6
at nodes N
1
and N
6
corresponding to an input pulse &PHgr;IN and synchronous pulses &PHgr;
1
, &PHgr;
2
.
First of all, when the synchronous pulse &PHgr;
1
is changed from a Low level (referred to as “L” hereinafter) to a High level (referred to as “H” hereinafter) at the time t
1
, the input pulse &PHgr;IN becomes “H”, and, hence, the potential VN
1
of the node N
1
is changed from “L” to “H” through a NNT
1
.
Assuming “L” of the input pulse &PHgr;IN and the synchronous pulses &PHgr;
1
, &PHgr;
2
having inverse phases from each other as a ground level (GND), and the “H” state of the input pulse &PHgr;IN and the synchronous pulses &PHgr;
1
, &PHgr;
2
as a threshold value Vth of V&PHgr;<NNT
1
, the potential VN
1
at this point of time can be substantially expressed by the following equation (1). Here, V&PHgr; indicates the voltage at the “H” level of the synchronous pulses &PHgr;
1
, &PHgr;
2
and NNT
1
indicates a MOS transistor.
VN
1
=V&PHgr;−Vth (1)
Even when the synchronous pulse &PHgr;
1
falls from “H” to “L” at the time t
2
, the input pulse &PHgr;IN remains at “H” level, and, hence, the output VN
1
holds the voltage expressed by the equation (1). In a strict sense, at a point of time at which the synchronous pulse &PHgr;
1
falls, the potential becomes lower than the voltage expressed by the equation (1) due to a capacitive coupling between a gate of the transistor NNT
1
and the node N
1
or the like. However, such a phenomenon is not essential in the explanation of the operation, and, hence, the phenomenon is ignored. Since the NNT
1
turns OFF, the node N
1
becomes a floating node.
Subsequently, when the synchronous pulse &PHgr;
2
is changed from “L” to “H” at the time t
2
, provided that the following equation (2) is satisfied,
V&PHgr;−Vth≧V&PHgr; (2)
The MOS transistor NNT
2
becomes the ON state and the pulse &PHgr;
2
enters the node N
2
. At this point of time, due to the coupled capacitance Cb
1
, which is referred to as a bootstrap capacitance that is inserted between the nodes N
1
and N
2
, a voltage rise on a point of the node N
2
is transmitted to the node N
1
which is in the floating state, so that the potential of the node N
2
also rises.
Assume that the rising potential of the node N
2
as &Dgr;VN
2
, the output VN
1
is given by a following equation (3):
VN
1
=(V&PHgr;−Vth)+&Dgr;VN
2
(
Cb/Cb
(
Cb+Cs
)) (3)
Here, the capacitance Cb includes, besides the capacitance shown in the circuit diagram, such as the preceding coupled capacitance CB
1
, all of the coupled capacitance of synchronous pulse &PHgr;
2
and the node N
1
, which include the capacitance generated by the gate, the drain and the source of the transistor NMT
2
, or an inversion layer (channel) formed below the gate, and further include the direct connection capacitance between the wiring of the synchronous pulse &PHgr;
2
and the node N
1
. Further, Cs indicates a capacitance obtained by subtracting the above-mentioned bootstrap capacitance Cb from the whole capacitance of the node N
1
and constitutes so-called parasitic capacitance.
Here, provided that a following equation (&PHgr;is satisfied at &Dgr;VN
2
V&PHgr;.
(V&PHgr;−Vth)+V&PHgr;(
Cb/Cb
(
Cb+Cs
))>V&PHgr;+Vth (4)
This implies that the gate voltage of the MOS transistor NMT
2
, that is, the output VN
1
, becomes higher than V&PHgr;+Vth. Accordingly, the output VN
2
can be set to the potential of the voltage V&PHgr;. By suitably selecting the capacitance Cb
1
, which constitutes a design element, it is easy to satisfy the above-mentioned equation (4), and, hence, the output VN
2
can be set to the potential of the voltage V&PHgr;.
Here, at the same time, the potential of the node N
3
takes a value expressed by a following equation (5) through a MOS transistor NMT
3
, which is subjected to the diode connection.
VN
3
=V&PHgr;Vth (5)
Since the MOS transistor NMT
3
is subjected to the diode connection, even when the synchronous pulse &PHgr;
2
is changed from “H” to “L” at the time t
3
, the state expressed by the above equation (5) can be held.
When the synchronous pulse &PHgr;
1
is changed from “L” to “H” at the time t
3
, an operation similar to that expressed by the equation (3) occurs at the node N
3
and a MOS transistor NMT
5
, so that the outputs VN
3
, VN
4
respectively generate the change of potential as schematically shown in FIG.
1
B.
Here, when the nodes N
2
, N
4
, N
6
are used as output nodes, shift pulses (VN
2
, VN
4
, VN
6
) having the potential equal to that of “H” of the synchronous pulse can be obtained, and the dynamic operation which does not generate a through-current can be performed, as apparent from the above-mentioned operations.
However, when the dynamic ratio register having such a constitution is formed by directly providing MIS transistors having semiconductor layers which are made of polycrystalline silicon (p-Si) to surfaces of substrates (glass substrates) which are arranged to face each other in an opposed manner through a liquid crystal, it has been confirmed that the dynamic ratio register operates in an extremely unstable manner, so that the cou
Goto Kazutaka
Hasegawa Atsushi
Maki Masashiro
Miyazawa Toshio
Takemoto Iwao
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Said Mansour M.
Shalwala Bipin
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