Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
1997-11-25
2002-07-09
Sikes, William L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S047000, C257S072000
Reexamination Certificate
active
06417896
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuits and elements for improving the image quality of the display screen of an active matrix type display device used in, for example, a liquid crystal display device, a plasma display device or an EL (electroluminescence) display device.
2. Description of the Related Art
FIG. 2A
schematically shows a conventional active matrix display device. A region
104
shown by the broken line is a display region. Thin film transistors (TFTs)
101
are arranged at a matrix form in the region
104
. The wiring connected to the source electrode of the TFT
101
is an image (data) signal line
106
, and the wiring connected to the gate electrode of the TFT
101
is a gate (selection) signal line
105
. A plurality of gate signal lines and image signal lines are arranged approximately perpendicular to each other.
An auxiliary capacitor
102
is used to support the capacitance of the pixel cell
103
and store image data. The TFT
101
is used to switch the image data corresponding to the voltage applied to the pixel cell
103
.
In general, if a reverse bias voltage is applied to the gate of a TFT, a phenomenon is known that a current does not flow between the source and the drain (the OFF state), but a leak current (the OFF current) flows. This leak current varies the voltage (potential) of the pixel cell.
In an N-channel type TFT, when the gate is negatively biased, a PN junction is formed between a P-type layer which produces at the surface of the semiconductor thin film and an N-type layer of the source region and the drain region. However, since there are a large number of traps present within the semiconductor film, this PN junction is imperfect and a junction leak current is liable to flow. The fact that the OFF current increases as the gate electrode is negatively biased is because the carrier density in the P-type layer formed in the surface of the semiconductor film increases and the width of the energy barrier at the PN junction becomes narrower, thereby leading to a concentration of the electric field and an increase in the junction leak. current.
The OFF current generated in this way depends greatly on the source/drain voltage. For example, it is known that the OFF current increases rapidly as the voltage applied between the source and the drain of the TFT increases. That is, for a case wherein a voltage of 5 V is applied between the source and the drain, and one wherein a voltage of 10 V is applied therebetween, the OFF current in the latter is not twice that of the former, but can be 10 times or even 100 times as large. This nonlinearity also depends on the gate voltage. If the reverse bias value of the gate electrode is large (a large negative voltage for an N-channel type), there is a significant difference between both cases.
To overcome this problem, a method (a multigate method) for connecting TFTs in series has been proposed, as in Japanese Patent Kokoku (examined) Nos. 5-44195 and 5-44196. This aims to reduce the OFF current of each TFT by reducing the voltage applied to the source/drain of each TFT. When two TFTs
111
and
112
are connected in series in
FIG. 2B
, the voltage applied to the source/drain of each TFT is halved. According to the above, if the voltage applied to the source/drain is halved, the OFF current is reduced to {fraction (1/10)} or even {fraction (1/100)}. In
FIG. 2B
, numeral
113
is an auxiliary capacitor, numeral
114
is a pixel cell, numeral
115
is a gate signal line, and numeral
116
is an image signal line.
However, as the properties required for the image display of a liquid crystal display device become more severe, it becomes difficult to reduce the OFF current sufficiently even using the above multigate method. This is because, even if the number of gate electrodes (the number of TFTs) is increased to 3, 4 or 5, the voltage applied to the source/drain of each TFT is only slightly reduced, to ⅓, ¼ or ⅕. There are additional problems in that the circuit becomes complicated and the occupied area is large.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a pixel circuit having a structure wherein the OFF current is reduced by decreasing the voltages applied to the source/drain of TFTs connected to the pixel electrode to less than {fraction (1/10)}, preferably less than {fraction (1/100)} of their normal value.
The present invention disclosed in the specification is characterized in that a structure includes gate signal lines and image signal lines arranged at a matrix form, pixel electrodes arranged in regions surrounded by the gate signal lines and the image signal lines, and thin film transistors (TFTs) (the number of TFTs is n) having the same conductivity type connected to each other in serial adjacent to each of the pixel electrodes, wherein a source region or a drain region of a first TFT (n=1) is connected to one of the image signal lines, a source region or a drain region of an nth TFT is connected to one of the pixel electrodes, at least one of two regions adjacent to a channel forming region of each of TFTs (the number of TFTs is n−m (n>m)) is a low concentration impurity region that an impurity concentration for providing a conductivity type is lower than the source or drain region, and a gate voltage each of TFTs (The number of TFTs is m) is maintained to a voltage that a channel forming region becomes the same conductivity type as that of the source and drain regions. In the above structure, n and m are a natural number except 0. To obtain a desired effect, it is preferred that n is 5 or more.
An example of the above structure is shown in FIG.
2
C. In
FIG. 2C
, five TFTs
121
to
125
are each arranged in series, that is, n=5 and m=2. The source region of the TFT
121
(n=1) is connected to an image signal line
129
. The drain region of nth TFTs
123
(n=5) is connected to the pixel electrode of a pixel cell
127
and an auxiliary capacitor
26
.
Gate electrodes of TFTs
121
to
123
(the number of TFTs is n−m (n>m) are connected to a common gate signal line
128
and each TFT has an LDD (lightly doped drain) structure and/or an offset structure. Gate electrodes of the other TFs
124
and
125
(the number of TFTs is m) are connected to a common capacitance line
130
. The capacitance line
130
is maintained at a desired voltage.
In
FIG. 2C
, the basic feature of the present invention is to connect the TFTs
121
to
125
in series, of these, to connect the gates of the TFTs
121
to
123
to the gate signal line
128
, and to connect the gates of the other TFTs
124
and
125
to the capacitance line
130
. Thus, for a period of time maintaining a voltage of a pixel, capacitors are formed between the channel and the gate electrode of each of the TFTs
124
and
125
by maintaining the capacitance line at a suitable voltage.
Thus the voltage between the source and the drain of each of the TFTs
122
and
123
is reduced, thereby decreasing the OFF current of the TFTs. An auxiliary capacitor is not absolutely necessary. Rather, since it increases the load during data writing, there are cases in which it is preferably not included, if the ratio between the capacitance of the pixel cell and that generated in the TFTs
124
and
125
is optimum.
To describe the action specifically with FIG.
2
C: when a selection signal is applied to the gate signal line
128
, all the TFTs
121
to
123
are turned on. In order for the TFTs
124
and
125
also to be ON, it is necessary to apply a signal to the capacitance line
130
. Thus, the pixel cell
127
is charged in accordance with a signal on the image signal line
129
, and at the same time the TFTs
124
and
125
are also charged. At the (equilibrium) stage when sufficient charging has performed, the voltages between the source and the drain of the TFTs
122
and
123
are approximately the same.
If, in this state, the selection signal is not applied or disconnected, the TFTs
121
to
Koyama Jun
Takemura Yasuhiko
Yamazaki Sunpei
Fish & Richardson P.C.
Nguyen Dung
Semiconductor Energy Laboratory Co,. Ltd.
Sikes William L.
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