Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-12-06
2003-09-30
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S090000, C345S098000
Reexamination Certificate
active
06628262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix type display apparatus, in which a display panel can be efficiently driven.
2. Description of the Related Art
An active matrix display represented by a TFT liquid crystal display is typically composed of a display panel, a drive circuit for driving the display panel, and a controller for sending display data to the drive circuit. The operating frequency of the drive circuit is set to be lower than that of the controller. The controller reduces the transfer rate of the display data in accordance with the operating frequency of the driving circuit to transfer the display data to the drive circuit.
Technique for reducing the transfer rate of display data is disclosed in Japanese Laid Open Patent Applications (JP-A-Showa 64-13193, JP-A-Heisei 6-18844 and JP-A-Heisei 10-207434).
In the technique of Japanese Laid Open Patent Application (JP-A-Showa 64-13193), a data signal is divided into an odd-numbered data signal and an even-numbered data signal in order to drive an EL panel. The odd-numbered data signal and the even-numbered data signal are transferred in parallel with each other in synchronism with a half of the frequency of a reference clock signal so as to carry out the display control pixel by pixel. This technique does not consider the drive of an active matrix display such as a liquid crystal panel. The pixel-by-pixel drive control can be carried out under the presumption that the EL panel is driven. However, it is difficult to use the pixel-by-pixel drive control for the drive control of the active matrix type display apparatus.
In the technique of Japanese Laid Open Patent Application (JP-A-Heisei 6-18844), the bit of a display data signal is doubled. The doubled display data is transferred in synchronism with a half frequency of a reference clock signal.
In the technique of Japanese Laid Open Patent Application (JP-A-Heisei 10-207434), a source driver of a display panel is divided into a first half portion and a second half portion, and a line memory is similarly divided into two portions. Two data stored in the line memory are simultaneously supplied to the first and second portions of the source driver in synchronism with a half frequency of a reference clock signal. In this reference, display data required for the display of one line is stored in the line memory. After the completion of storing of the display data in the line memory, the display data for one line is simultaneously supplied to the display panel. In other words, this technology requires a line memory to have a capacity enough to store the display data for one line.
In this way, in the conventional active matrix type display apparatus, the operating clock of the drive circuit for driving the display panel can be set to be a half frequency of the reference clock signal. However, in order to perform frequency division of the clock, the arrangement of elements inevitably becomes complicated and a large capacity of memory is required. The large capacity of memory is equivalent to the memory having a capacity large enough to store display data for one line, for example, as in the technology disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-207434).
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an active matrix type display apparatus in which the storage capacity of a memory for temporarily storing display data can be significantly reduced.
Another object of the present invention is to provide an active matrix type display apparatus having good EMI characteristics.
In order to achieve an aspect of the present invention, an active matrix type display apparatus includes a display panel, a horizontal display driver and a controller. The horizontal display driver includes m (m is an integer larger than 1) horizontal driving sections to drive the display panel based on m display data sets in response to an output clock signal, respectively. The controller generates the output clock signal from an input clock signal, and carries out sampling of input data to produce display data for a horizontal line of the display panel. Also, the controller sequentially stores the display data and outputs the stored display data to the m horizontal driving sections in units of display data sets in response to the output clock signal, respectively.
Here, the controller may include a clock signal generating section which generates the output clock signal from the input clock signal. In this case, a frequency of the output clock signal is larger than that of the input clock signal.
Also, the output clock signal may include n (n is an integer larger than 1) clock signals, each of the m horizontal driving sections may include n driving sections, and the display data set may include n display data portions. At this time, the n driving sections drive the display panel based on the n display data portions of the display data set corresponding to the n driving sections in response to the n clock signals, respectively. In this case, n may be 2. In this case, the output clock signal may include first and second clock signals which are different in phase from each other by 180 degrees.
Also, the controller may include a dual port memory which sequentially stores the display data and outputs the stored display data to the m horizontal driving sections in units of display data sets in response to the output clock signal, respectively. In this case, it is desirable that the dual port memory operates in a first-in and first-out manner.
In order to achieve another aspect of the present invention, an active matrix type display apparatus includes a display panel, a horizontal display and a controller. The horizontal display driver includes m (m is an integer larger than 1) horizontal driving sections to drive the display panel based on m display data sets in response to an output clock signal, respectively. The controller generates the output clock signal from an input clock signal, and a frequency of the output clock signal is larger than that of the input clock signal. Also, the controller carries out sampling of input data to produce display data for a horizontal line of the display panel, and outputs the display data to the m horizontal driving sections in units of display data sets in response to the output clock signal, respectively.
Here, the output clock signal may include n (n is an integer larger than 1) clock signals, each of the m horizontal driving sections may include n driving sections, and the display data set may include n display data portions. At this time, the n driving sections drive the display panel based on the n display data portions of the display data set corresponding to the n driving sections in response to the n clock signals, respectively. In this case, n may be2. In this case, the output clock signal may include first and second clock signals which are different in phase from each other by 180 degrees.
Also, the controller may include a dual port memory which sequentially stores the display data and outputs the stored display data to the m horizontal driving sections in units of display data sets in response to the output clock signal, respectively. In this case, it is desirable that the dual port memory operates in a first-in and first-out manner.
In order to achieve still another aspect of the present invention, an active matrix type display apparatus includes a display panel, a horizontal display driver and a controller. The horizontal display driver set includes m (m is an integer larger than 1) horizontal driving sections to drive the display panel at different timings based on m display data sets in response to an output clock signal, respectively. The controller generates the output clock signal from an input clock signal, and a frequency of the output clock signal being larger than that of the input clock signal. Also, the controller carries out sampling of input data to produce display data for a horizontal line of the display panel, and outputs the
Dinh Duc Q.
Hjerpe Richard
NEC LCD Technologies Ltd.
Young & Thompson
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