Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1998-06-26
2001-10-02
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S350000, C349S043000, C349S044000
Reexamination Certificate
active
06297518
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix display construction and, more particularly, to a circuit and device structure for improving the quality of the image displayed on the viewing screen.
2. Description of the Related Art
FIG.
2
(A) schematically shows a conventional active matrix display. In this figure, the region
204
surrounded by the broken line is a display region. Thin-film transistors
201
(only one is shown) are arranged in rows and columns in this region
204
. Conductive interconnects connected with the source electrodes of the thin-film transistors
201
are image signal lines or data signal lines
206
. Conductive interconnects connected with the gate electrodes of the thin-film transistors
201
are gate-selecting signal lines
205
(only one is shown).
We now take notice of driver devices. The thin-film transistors
201
act to switch data, and drive a liquid-crystal cell
203
. Auxiliary capacitors
202
(only one is shown) are used to reinforce the capacitance Qf the liquid-crystal cell, and act to hold image data. The thin-film transistors
201
are employed to switch image data indicated by the voltage applied across the liquid-crystal material. Let V
GS
be the gate voltage of each thin-film transistor. Let I
D
be the drain current. The relation V
GS
-I
D
is shown in FIG.
3
. In particular, if the gate voltage V
GS
is in the cutoff region of the thin-film transistor, the drain current I
D
is increased, and it is called OFF current.
In the case of an N-channel thin-film transistor, the OFF current flowing when the gate voltage V
GS
is biased negatively is stipulated by the current flowing through a PN junction formed between a P-type layer and an N-type layer. The P-type layer is induced in the surface of the thin-film semiconductor. The N-type layer is formed in the source and drain regions. Because numerous traps exist in the thin-film transistor, this PN junction is incomplete and so the junction tends to produce a leakage current. As the gate electrode is biased more negatively, the OFF current is increased, for the following reason. The concentration of carriers in the P-type layer formed in the surface of the thin-film semiconductor is increased, thus reducing the width of the energy barrier in the PN junction. As a result, the electric field is concentrated, so that the current leaking from the junction increases.
The OFF current produced in this way depends greatly on the source/drain voltage. For example, it is known that as the voltage applied between the source and drain of a thin-film transistor is increased, the OFF current is increased drastically. That is, the OFF current produced when a voltage of 10 V is applied is not merely twice as large as the OFF current produced when a voltage of 5 V is applied between the source and drain. Rather, the ratio of the former OFF current to the latter OFF current reaches 10 or even 100. This nonlinearlity also depends on the gate voltage. Generally, where the reverse bias applied to the gate electrode is large (in the case of an N-channel type, a large negative voltage), the ratio is large.
In an attempt to solve this problem, the multi-gate method has been proposed as described in Japanese Patent Publication Nos. 44195/1993 and 44196/1993. In this method, thin-film transistors are connected in series. This method is intended to reduce the OFF current of each individual thin-film transistor, by reducing the voltage applied between the source and drain of each thin-film transistor. For example, where two thin-film transistors are connected in series as shown in FIG.
2
(B), the voltage applied between the source and drain of each thin-film transistor is halved. This reduces the OFF current by a factor of 10 or even 100 because of the principle described above.
TFTs, source lines, and gate lines are formed in an active matrix circuit. These elements hinder transmission of light. Specifically, the ratio (aperture ratio) of the area of the region that can be used for image display to the whole area is small. Typically, the aperture ratio is 30 to 60%. Especially, in a backlit display device comprising an active matrix circuit backlit with intense light, if the aperture ratio is small, a major portion of the incident light is absorbed by TFTs and by the liquid-crystal material and so these TFTs and liquid-crystal material get hot. As a result, their characteristics are deteriorated.
However, as the image displayed on a liquid crystal display is required to have stricter characteristics, it is more difficult to reduce the OFF current by a required amount by the aforementioned multi-gate method. In particular, if the number of the gate electrodes (or, the number of thin-film transistors) is increased to 3, 4, and 5, then the voltage applied between the source and drain of each TFT decreases to one-third, one-fourth, and one-fifth, respectively. In this way, the latter voltage does not decrease rapidly. Therefore, in order to reduce the voltage between the source and drain by a factor of 100, as many as 100 gates are needed. That is, in this method, the resulting advantage is most conspicuous where the number of gates is two. However, if more gates are provided, great advantages cannot be expected.
SUMMARY OF THE INVENTION
In view of the foregoing problems, the present invention has been made.
It is an object of the invention to provide a pixel circuit which reduces the voltage applied between the source and drain of each TFT (thin-film transistor) connected with a pixel electrode down to a level which is about less than one-tenth, preferably less than one-hundredth, of the level normally obtained, thus reducing the OFF current. This pixel circuit is characterized in that the number of TFTs used for the above-described object is reduced sufficiently. Preferably, the number of the TFTs is less than 5, more preferably 3.
It is another object of the invention to provide an active matrix display comprising TFTs which are prevented from being irradiated with light without lowering the aperture ratio.
The theory underlying the inventive concept is illustrated in FIG.
2
(C), where TFTs (thin-film transistors)
221
and
222
are connected in series. A capacitor
223
is inserted between these TFTs
221
and
222
to lower the voltage produced between the source and drain of the TFT
222
especially located on the side of a pixel electrode. This reduces the OFF current of the TFT
222
. The illustrated capacitor
224
is not always necessary. Rather, this capacitor
224
increases the burden imposed during writing. Therefore, if the ratio of the capacitance of a pixel cell
225
to the capacitance
223
is appropriate, then it may be desired to dispense with the capacitor
224
.
The operation is next described in detail. When a select signal is sent to a gate signal line
226
, both TFTs
221
and
222
are turned ON. Depending on the signal on an image signal line
227
, the capacitors
223
,
224
and the pixel cell
225
are electrically charged. When they are fully charged, i.e., when a balanced state is obtained, the voltage applied to the source of the TFT
222
is substantially equal to the voltage applied to the drain of the TFT
222
.
Under this condition, if the select signal is made to cease, both TFTs
221
and
222
are turned OFF. Then, a signal for other pixel is applied to the image signal line
227
. The TFT
221
produces a finite amount of leakage current. Consequently, the electric charge stored in the capacitor
223
is released, so that the voltage drops but at a rate roughly equal to the rate at which the voltage developed across the capacitor
202
of the normal active matrix circuit shown in FIG.
2
(A) drops.
On the other hand, with respect to the TFT
222
, the. voltage developed between the source and drain is initially almost zero. For this reason, the OFF current is quite weak. Then, the voltage developed across the capacitor
223
drops. Therefore, the voltage between the source and drain increases gradually. This,
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
Tran Minh Loan
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