Active matrix devices

Details Active matrix devices Active matrix devices

1998-04-03

2002-08-20

Saras, Steven (Department: 2675)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S098000, C345S696000

Reexamination Certificate

active

06437767

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to active matrix devices and is concerned more particularly, but not exclusively, with driver circuits for active matrix liquid crystal displays (AMLCD's).
The invention can be applied, for example, to driver circuits of AMLCD's to be implemented in separate large scale integration (LSI) driver chips, or to be integrated on the display substrate in the form of thin film transistors (TFT) using silicon-on-insulator (SOI) technology. Furthermore the invention can be applied to analogue displays which are supplied with analogue RGB video data, or to digital displays which contain digital-to-analogue (D/A) converters and which have a completely digital interface.
DESCRIPTION OF THE RELATED ART
FIG. 1
shows a typical AMLCD
1
composed of N rows and M columns of pixels addressable by scan lines
2
connected to a scan line driver circuit
3
and data lines
4
connected to a data line driver circuit
5
. Data voltages are applied to the data lines
4
by the data line driver circuit
5
and scan voltages are applied to the scan lines
2
by the scan line driver circuit
3
so that such voltages in combination serve to apply analogue data voltages to the pixel electrodes
6
in order to control the optical transmission states of the pixels along each row as the rows are scanned in a cyclically repeating sequence. This is achieved as follows for a single row of pixels. The data line driver circuit
5
reads a line of data to be displayed by the row of pixels and applies corresponding data voltages to the data lines
4
so as to charge up each data line
4
to the required data voltage. The scan line
2
corresponding to the row of pixels to be controlled is activated by the application of the scan voltage by the scan line driver circuit
3
so that a TFT
7
associated with each pixel is switched on to transfer charge from the corresponding data line
4
to a pixel storage capacitance
8
(as shown in broken lines in the figure) associated with the pixel. When the scan voltage is removed the TFT
7
isolates the pixel storage capacitance
8
from the data line
4
so that the optical transmission state of the pixel corresponds to the voltage across the pixel storage capacitance
8
until the pixel is refreshed during the next scanning frame. The rows of pixels are refreshed one at a time until all the rows have been refreshed to complete refreshing of a frame of display data. The process is then repeated for the next frame of data.
In the case of analogue displays, the display data is supplied to the data line driver circuit in the form of an analogue video (AVIDEO) signal which is sampled at a frequency dependent on the resolution and frame rate of the display, the sampling frequency (also referred to as the pixel data rate) being equal to fNM where f is the frame rate of the display.
For analogue displays of small size or low pixel resolution, a point-at-a-time data line driver circuit
10
is commonly employed for the data line driver circuit, as shown in FIG.
2
. In this circuit
10
a sampling shift register
11
composed of a chain of D-type flip-flops is connected so that the output of each flip-flop controls the gate of an associated sampling transistor
12
for applying the AVIDEO signal to the corresponding data line
4
with its associated parasitic capacitance shown in broken lines at
13
in the figure. The key feature of such a point-at-a-time driving scheme is that the sampling transistors
12
are directly connected to the data lines
4
. In operation frame and line synchronisation pulses VSYNC (not shown) and HSYNC indicate the start of a frame period and a line period respectively, and a clock signal CK at the sampling frequency is applied to the clock inputs of the flip-flops so that a circulating “1” state within the shift register sequentially activates the sampling transistors
12
at the sampling frequency. The RC time constant formed by the resistance of the sampling transistor
12
and the data line
4
(which may have a resistance of several thousand Ohms). and the distributed capacitance of the data line (which may amount in total to tens of picofarads) must be sufficiently less than the available sampling period (1/fNM) for the sampling to be executed successfully.
FIG. 3
is a timing diagram showing the timing of the signals associated with such a point-at-a-time data line driver circuit, where S
1
, S
2
and S
3
refer to the scan voltages applied to the first three scan lines numbered from the top of the display. It will be noted that the AVIDEO signal is sampled at the same time as application of the data voltages to the pixels on activation of the scan lines in successive scanning line periods T
1
, T
2
. . . by the scan voltages S
1
, S
2
, S
3
, such scan voltages being synchronised by the HSYNC pulses. However, since the TFT associated with each pixel of the row is turned on while the data for that row is being sampled onto the data lines
4
, the pixels towards the right hand side of the display will be charged with the sampled voltage over an effective scan time which is much less than the line period. Indeed, in the worst case, the effective scan time may be little more than the HSYNC pulse period.
For analogue displays of large size or high pixel resolution, the data lines will be both more capacitative and more resistive so that the available sampling period (1/fNM) is too small for the sampling transistor to charge up the data line directly, and the sampling must therefore be buffered. For analogue displays, a small capacitor, which can be charged or discharged very quickly, can be located within each column of the data drive circuit so as to store samples of the AVIDEO signal. The data voltage can then be transferred to each data line by a buffer circuit. However this transfer operation may take several microseconds and this again puts constraints on the time available to scan the right hand side pixels of the display.
FIG. 4
shows at (a) a typical analogue line-at-a-time data line driver circuit
20
such as is more commonly used for buffered sampling, the circuit
20
comprising a sampling shift register
11
comprising a chain of D-type flip-flops as before, but with the outputs of the flip-flops connected to sampling circuits comprising two sets of capacitative memory elements
21
and
22
and line drivers
23
for driving the data lines.
FIG. 4
shows at (b) and (c) two alternative circuit arrangements for such a data line driver circuit
20
in which the two sets of memory elements comprise two capacitors
25
,
26
or
27
,
28
and associated switches
25
A,
26
A, or
27
A,
27
B,
28
A,
28
B for each data line and the line drivers comprise a buffer
29
or
30
for each data line, as will be described in more detail below.
FIG. 5
shows a timing circuit for such a line-at-a-time data line driver circuit for comparison with the timing circuit of the point-at-a-time data line driver circuit of FIG.
3
. The important feature of the line-at-a-time driving scheme is that the scan line is activated only after a complete line of data has been sampled during a line period T
1
, the next complete line period T
2
being used for scanning of the data to the pixels as well as sampling of the data for the next row of pixels. Because sampling and data line driving cannot occur simultaneously, each sampling circuit includes two sets of memory elements
21
and
22
as shown in FIG.
4
(
a
). In the first circuit arrangement of FIG.
4
(
b
), each capacitor
25
is used for sampling a corresponding point in a line of data and its charge is then shared with the capacitor
26
. The capacitor
26
and buffer
29
are then used to drive the data line, leaving the capacitor
25
free to sample a corresponding point in the next line of data. In the second circuit arrangement of FIG.
4
(
c
), on the other hand, the capacitor
27
is used for sampling a corresponding point in a line of data while the capacitor
28
and buffer
30
are driving the data line. During the next line pe

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