Active matrix circuit

Details Active matrix circuit Active matrix circuit

1999-08-17

2003-04-22

Dudek, James (Department: 2871)

Liquid crystal cells, elements and systems

Particular excitation of liquid crystal

Electrical excitation of liquid crystal

C349S042000, C349S139000, C257S072000

Reexamination Certificate

active

06552758

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active matrix circuit which is used for display with a liquid crystal, and other purposes.
2. Description of the Related Art
FIG. 6
schematically shows an example of a conventional active matrix display device. In a display area which is enclosed by a broken line in
FIG. 6
, transistors Tr as switching elements are arranged in matrix form such that a single transistor is provided for each matrix element. When attention is paid to an nth-row/mth-column element of the matrix, an image (data) signal line Y
m
is connected to the source of the transistor Tr and a gate (selection) signal line X
n
is connected to the gate electrode of the transistor Tr.
Attention is now paid to the transistor as the switching element, which performs data switching and drives a liquid crystal cell LC. An auxiliary capacitor C, which supplements the capacitance of the liquid crystal cell LC, is used to hold image data. The transistor Tr switches image data, i.e., a voltage, to be applied to the liquid crystal. The most serious problem in using a transistor as s switching element is leak current (or off-current) that flows in a state that no selection pulse is applied to the gate (non-selection state). If the leak current is large, the amount of charge stored in the pixel electrode and the auxiliary capacitor easily decreases, resulting in deterioration in display performance.
SUMMARY OF THE INVENTION
An object of the invention is therefore to provide an active matrix circuit having small off-current.
According to the invention, a switching element is provided which is a series connection of a plurality of transistors. One end of the switching element is connected to a data signal line and the other end is connected to a pixel electrode. The respective transistors are controlled by independent gate signal lines. Connecting the transistors in series is effective in reducing the leak current.
More specifically, according to a first aspect of the invention, there is provided an active matrix circuit including first and second switching elements provided adjacent to each other and connected to the same data signal line and first to third gate (selection) signal lines that are adjacent to each other. The first switching element is controlled by the first and second gate signal lines while the second switching element is controlled by the second and third gate signal lines.
According to a second aspect of the invention, there is provided an active matrix circuit including first and second switching elements provided adjacent to each other and connected to the same data signal line and first to fourth gate (selection) signal lines that are adjacent to each other. The first switching element is controlled by the first and second gate signal lines while the second switching element is controlled by the third and fourth gate signal lines. The same signal is applied to the second and third selection signal lines.
FIGS. 1A and 1B
are circuit diagrams showing the above-described first and second aspects of the invention, respectively. In these figures, a portion enclosed by a broken line corresponds to a pixel unit. In each of
FIGS. 1A and 1B
, each switching element consists of two transistors Tr
1
and Tr
2
, which are controlled by different gate signal lines. In the case of
FIG. 1B
, two gate signal lines X
n
and Z
n
are provided for each row. However, as shown in
FIG. 1B
, the gate signal line Z
n
and a gate signal line X
n+1
of the next row are connected to each other outside the matrix, and therefore supplied with the same signal.
In each of the first and second aspects of the invention, an auxiliary capacitor C may be provided as in the conventional case of FIG.
6
. However, although in the conventional case a capacitor can be formed between the pixel electrode and the gate signal line X
n+1
adjacent thereto as shown in
FIG. 7
, such a configuration is not preferable in the invention. This is because in the invention the gate signal line adjacent to the pixel electrode is the one for driving the pixel concerned, and therefore in the above configuration the potential of the pixel electrode would vary (called a through voltage drop) in accordance with on/off switching of a selection pulse.
Therefore, in the invention, it is preferred that an auxiliary capacitor be formed between the pixel electrode and a wiring line other than the gate signal line. For example, a capacitor may be provided such that a light-shielding layer is formed with a conductive material so as to overlap with the pixel electrode and is kept at a constant potential. Alternatively, as shown in
FIG. 1C
, a capacitor may be provided by forming an overlap between an intermediate portion of the transistors Tr
1
and Tr
2
and the gate signal line for controlling the transistor Tr
2
. In this case, it is not preferable to provide a capacitor between the intermediate portion and the gate signal line for controlling the transistor Tr
1
for a reason described later. In
FIG. 1C
, an auxiliary capacitor C is provided in the circuit of FIG.
1
A. An auxiliary capacitor may also be provided in the circuit of
FIG. 1B
in a similar manner.
As is derived from the above discussion, in the first aspect of the invention, pulses applied to the first and second gate signal lines overlap in time with each other and, similarly, pulses applied to the second and third gate signal lines overlap in time with each other. If pulses applied to the first and second gate signal lines did not overlap in time with each other, the transistors Tr
1
and Tr
2
could not be turned on at the same time and hence the pixel electrode could not be charged.
Similarly, in the second aspect of the invention, pulses applied to the first and second gate signal lines overlap in time with each other and pulses applied to the third and fourth gate signal lines overlap in time with each other, in which the same pulse is applied to the second and third gate signal lines.
FIGS. 2A and 2B
illustrate the above relationship. In
FIGS. 2A and 2B
, symbols V
n
represents a voltage waveform of the gate signal line X
n
in
FIG. 1A and D
m
represents a voltage waveform of the data signal line Y
m
. As seen from
FIGS. 2A and 2B
, pulses of V
n
and V
n+1
overlap with each other and pulses of V
n+1
and V
n+2
overlap with each other, and a pulse of D
m
in an overlapping period is written to the pixel electrode concerned; that is, a pulse D(Z
n, m
) is written to the pixel Z
n,m
and a pulse D(Z
n+1, m
) is written to the pixel Z
n+1, m
. For comparison, V
n
is also shown on V
n+2
and D
m
by a broken line.
FIG. 2A
shows a case where selection pulses are sequentially applied to the gate signal lines from the top; in more general terms, a selection pulse is applied to the transistor Tr
1
that is connected to the data signal line earlier than to the transistor Tr
2
(the transistor Tr
1
turns on or off earlier than the transistor Tr
2
).
FIG. 2B
shows a case where selection pulses are sequentially applied to the gate signal lines from the bottom; that is, a selection pulse is applied to the transistor Tr
2
that is connected to the pixel electrode earlier than to the transistor Tr
1
(the transistor Tr
2
turns on or off earlier than the transistor Tr
1
). In the case of
FIG. 2B
, the data signal D
m
may have a waveform of FIG.
2
C.
Where a capacitor is formed between the intermediate portion of the transistors Tr
1
and Tr
2
and a particular gate signal line as shown in
FIG. 1C
, it should be taken into consideration that the capacitor does not work as an auxiliary capacitor in the operation mode where selection pulses are applied to the gate signal lines from the bottom.
For example, a consideration will be made of the operation mode of FIG.
2
B. As for the pixel Z
n, m
, naturally data D(Z
n, m
) is written to this pixel in a state that both transistors Tr
1
and Tr
2
are on. Then, the transistor Tr
2
is turned off while the transist

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