Active matrix array devices

Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix

Reexamination Certificate

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Details

C345S092000

Reexamination Certificate

active

06703994

ABSTRACT:

The present invention relates to an active matrix array device comprising an array of individually addressable matrix elements, first and second sets of crossing address conductors connected to the matrix elements, the array of matrix elements and the sets of address conductors being carried on a substrate, and an addressing circuit connected to the sets address conductors for addressing the matrix elements and comprising a multiplexing circuit integrated on the substrate which is connected to address conductors of the first set and has a plurality, n, of signal bus lines, the address conductors of the first set being arranged in a series of groups with each group comprising n successive address conductors and the multiplexing circuit being arranged to couple sequentially each group of address conductors to the signal bus lines with each address conductor in a group being associated with and coupled to a respective one of the bus lines, the addressing circuit further including a respective signal processing circuit connected to each bus line.
The matrix array device may, for example, be an active matrix liquid crystal display device (AMLCD). Such a device typically comprises an array of liquid crystal display elements each of which is connected to the output of a respective TFT (thin film transistor) to which gating (selection) and data (video information) signals are supplied by respective row and column conductors. The addressing circuit consists of a row drive circuit connected to the row conductors for applying a gating signal to each row conductor in sequence to turn on the TFTs of each row of display elements in turn in respective row address periods and a column drive circuit connected to the set of column conductors for applying data signals to the column conductors in synchronism with scanning of the row conductors whereby the display elements of a selected row are charged via their respective TFTs to a level dependent on the value of the data signal existing on their associated column conductors to produce a required display effect. The TFTs usually comprise either amorphous silicon (a-Si) TFTs or polysilicon TFTs.
Beneficially, parts of the row and/or column drive circuits can be integrated on the substrate peripherally of the display element array using the same large area electronics technology as that employed for the active matrix circuitry of the array. For such purposes, the column drive circuit is customarily provided in the form of a simple multiplexing circuit, whose operation is based on a multiplexing technique in which the video information (data) is sequentially transferred via multiplexing switches from a plurality of video input bus lines, to which video information is applied simultaneously, to corresponding groups or blocks of column conductors in the display with each column conductor in a group being connected via a multiplexer switch to a different video input bus line. When using polysilicon TFT technology, this circuit is usually an analogue multiplexing type comprising groups of multiplexing switches, e.g. TFTs or CMOS gates, and a control circuit (normally comprising a shift register) which controls the operation of the multiplexer switches. Groups of video samples, constituting the data, taken from an input video signal are applied to the video bus lines and the data is then transferred to the relevant groups of column conductors in the display array during a video line period, which corresponds to a row address period.
When using digital video information, for example from a PC or other source, such information needs to be converted into analogue voltage levels usable by the display elements by DACs (Digital to Analogue Converter circuits). If such signal processing circuits were also integrated on the substrate, with their outputs connected to respective ones of the bus lines, then this further integration of additional components of the address circuitry would further simplify manufacture, thereby reducing cost, and would lead to a more compact arrangement with the number of external connections required being fewer.
However, experience has shown that the integration addressing circuitry, and particularly the integration of such processing circuits, can lead to display problems in the form of highly noticeable non-uniformities in the display output produced.
It is one object of the present invention to provide an active matrix array device with improvement in this respect.
According to the present invention, there is provided an active matrix array device of the kind described in the opening paragraph which is characterised in that the order in which the address conductors are associated with the signal bus lines in adjacent groups is mirrored. Thus, for example, if the first and nth address conductor in one group are coupled (via their respective multiplexing switches) to the first and nth signal bus lines respectively, then the first and nth address conductor in the adjacent group(s) are coupled to the nth and first signal bus lines respectively.
The mirroring of the physical arrangement of the couplings between the address conductors and the signal bus lines in adjacent groups means that the last address conductor in one group and the first, and physically adjacent, address conductor in the next group share the same signal bus line, and consequently the same signal processing circuit. This is beneficial to avoiding problems caused by any differences in the characteristics of the signal bus lines, for example due to their physical arrangement and the possibility of unwanted coupling of signals onto one line through parasitic capacitive coupling effects with adjacent lines and the like which then affect the data signals supplied by that signal bus line to its associated address conductors. More especially, it is important also to overcoming the aforementioned problems with display non-uniformity, particularly when the signal processing circuits associated with the bus lines are also integrated on the same substrate and fabricated from thin film circuit elements. It has been recognised that such display problems can result due to deficiencies in the operational characteristics of circuit elements when using thin film circuit components, such as TFTs and capacitors, for such purposes. In large area, thin film technology devices, the operational characteristics of individual thin film components such as TFTs will normally be similar where the components are formed physically close together but can vary significantly in the case of components formed further apart due, for example, to slight variations over the area of the device in the thicknesses and characteristics of individual deposited layers. With the n signal processing circuits associated with the n signal bus lines arranged physically juxtaposed in a line on the substrate for example, the operational behaviour of the first and last processing circuits may then differ significantly. If, therefore, successive signal processing circuits, for example, are simply connected in corresponding manner to the signal bus lines and the address conductors in each of the groups are connected to the bus lines in the same, repetitive and symmetrically identical, fashion, then it will be appreciated that the adjacent, last and first, address conductors in two adjacent groups will be associated respectively with the last and first signal processing circuits. Consequently any differences in the performance of these two processing circuits in view of the fact that they are widely separated will be highly noticeable as the matrix elements they serve are immediately adjacent one another. In the case for example of the device comprising an active matrix display device, such as in AMLCD, and the signal processing circuits comprising DAC circuits arranged juxtaposed, then variation in the analogue output voltages provided by the first and last converters to their respective bus lines, (associated with the first and last column conductors in one group,) will likely be the greatest due to them being the furth

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