Patent
1987-08-05
1989-03-21
Larkins, William D.
357 2312, 357 51, H01L 2704, H01L 2980
Patent
active
048148350
ABSTRACT:
An active load in an integrated logic circuit of the Direct Coupled FET Logic (DCFL type) in which the active load has a negative threshold voltage and the transistors have a positive threshold voltage. The active load is a transistor, the gate metallization of which is combined with the source metallization. If the active load delivers an excessive current, this current can be adjusted by adding at least one second gate which has a positive threshold voltage and which is in electrical contact with the first gate with a negative threshold voltage. The appropriate threshold voltages are obtained by bombarding the corresponding gate regions. The transistors of the integrated circuit are obtained during the manufacture of the second gate.
REFERENCES:
patent: 4255674 (1981-03-01), Grenier et al.
patent: 4402127 (1983-09-01), Pham et al.
patent: 4485390 (1984-11-01), Jones et al.
patent: 4628338 (1986-12-01), Nakayama
patent: 4709251 (1987-11-01), Suzuki
Proceedings of the IEEE, vol. 70, No. 1, Jan. 1982, pp. 35-45, IEEE, New York, U.S.; S. I. Long et al.: "High Speed GaAs Integrated Circuits".
"Thomson-CSF"
Larkins William D.
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