Active hierarchical bitline memory architecture

Details Active hierarchical bitline memory architecture Active hierarchical bitline memory architecture

1995-06-07

1999-11-16

Yoo, Do Hyun

Static information storage and retrieval

Interconnection arrangements

365190, 365203, 365207, G11C 700

Patent

active

059869143

ABSTRACT:
In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well. Interface circuitry is modified to provide voltage and signal gain and/or provide isolation between the local bitlines and the master bitlines, thereby reducing the amount of capacitance which must be driven by memory cells and the amount of time required to develop differential signals on the master bitlines.

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