1989-06-13
1991-03-26
James, Andrew J.
357 234, 357 41, 357 46, 357 59, 357 51, 357 55, H01L 2968, H01L 2910, H01L 2702
Patent
active
050033611
ABSTRACT:
A dynamic memory cell comprises a storage transistor and an access transistor. The gate of the storage transistor is utilized as storage capacitor electrode, and is connected to its source by a high resistor. The drain of the storage is connected to a source of electrical potential (e.g., V.sub.CC). The access transistor connects the source of the storage transistor to a bit line. This arrangement multiplies the effective capacitance of the gate storage capacitor, reducing the area required and hence making the structure more compact than a typical inactive (one transistor) DRAM cell. In a preferred embodiment, the resistor is formed to overlie the storage transistor, and the drain of the storage transistor is connected to V.sub.CC by means of the sidewall of a trench formed in the semiconductor substrate.
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AT&T Bell Laboratories
Fox J. H.
James Andrew J.
Ngo Ngan Van
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