Active delay line circuit

Details Active delay line circuit Active delay line circuit

1988-08-02

1990-02-06

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307481, 307479, 307602, 307590, 328 55, H03K 5159, H03K 513

Patent

active

048990710

ABSTRACT:
A digital delay circuit that can be readily implemented in an integrated circuit is disclosed. The circuit includes a reference clock and two or more arrays of controlled delay elements. The reference clock is passed through one array of delay elements and the thus-delayed clock is compared to an undelayed clock in a phase detector or comparator the output of which is a control voltage. The latter is applied to the control inputs of each of the delay elements. The controlled delay elements may be in the form of buffers in which the delay is varible and controlled by the level of the control input.

REFERENCES:
patent: 3737673 (1973-06-01), Suzuki
patent: 3855549 (1974-12-01), Huener et al.
patent: 3914702 (1975-10-01), Gehweiler
patent: 4532439 (1985-07-01), Koike
patent: 4700089 (1987-10-01), Fujii et al.
patent: 4771196 (1988-09-01), Mead et al.
patent: 4837466 (1989-06-01), Kanauchi

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