Active deassertion circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

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Details

323315, 327322, 327575, G05F 146

Patent

active

053629914

ABSTRACT:
An active deassertion circuit is a device that prevents signal lines used with a communications protocol from drawing too much current. Thus, the device prevents the driver(s) of the signal lines from malfunctioning and/or being damaged. The active deassertion circuit is comprised of a voltage regulator, with peripheral connections, coupled to a transistor that is used to sink excess current. The function of these elements ensures that no asserted signal line draws too much current if another signal line is actively deasserted. A method of using the active deassertion circuit is also disclosed.

REFERENCES:
patent: 3619659 (1971-09-01), Meyer
patent: 4339677 (1982-07-01), Hoeft
patent: 4434403 (1984-02-01), Chang
patent: 4536667 (1985-08-01), Masuda
patent: 4831283 (1989-05-01), Newton
patent: 4920339 (1990-04-01), Friend et al.
patent: 5010293 (1991-02-01), Ellersick
patent: 5027004 (1991-06-01), Palara
patent: 5028820 (1991-07-01), Sullivan
patent: 5072169 (1991-12-01), Saul et al.
patent: 5182526 (1993-01-01), Nelson
patent: 5239559 (1993-08-01), Brach et al.
Texas Instruments' publication (pp. 3, 4).

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