Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1999-11-19
2001-05-08
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S309000, C327S328000
Reexamination Certificate
active
06229372
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to active clamp circuits for clamping more than one voltage level useful for reducing electrical overshoot and undershoot, for minimizing ringing and similar noise problems, for providing electrostatic discharge (ESD) protection, particularly in high speed metal oxide semiconductor (MOS) and silicon-on-insulator (SOI) integrated circuit applications.
2. Description of Related Art
A computer comprises a multitude of circuits which need to electrically interact with each other and with circuits external to the computer via signals on cables. These external circuits may be contained in other computers, memory storage devices, input/out devices, networks, etc. The signals are in the form of digital ones and zeroes which merely represent voltage levels on the cables. As computers evolve, the voltage levels have decreased so that a digital one which was once 5 volts is now 3.3. volts, 1.8 volts, 1.2 volts and even lower. Moreover, circuits operating at one voltage level may need to transfer signals to and/or receive signals from circuits operating at other voltage levels; or an integrated circuit card may need to be replaced and the replacement card may operate at a different, usually lower, voltage level. A special circuit called a clamping circuit partially terminates and protects each circuit from voltages that are outside its operating range.
Clamping circuits maintain voltages of an electronic circuit within an acceptable range, that is, clamping circuits control electrical overshoot when a voltage exceeds an upper limit and undershoot when voltages decrease below a lower limit at the signal input of a digital circuit to provide a reliable logic signal under adverse and noisy conditions. Ideally the input voltage to each element in a digital circuit will be in only one of two distinct logic states, either an upper digital voltage or a lower digital voltage, corresponding to the digital ones and zeros of the circuit. As mentioned and as used in the following discussion, the positive terminal of the power supply will be referred to as Vdd. In older designs, this voltage is typically +5 volts, however, in newer designs, it may be 3.3, 2.5, 1.8, 1.2 volts or even lower. The lower voltage terminal of the power supply is referred to as Vss, and this voltage is usually at ground potential which may be zero volts. In an ideal system, the input voltage switches instantly between the high voltage state, a digital one, and the low voltage state, a digital zero, never going above the upper voltage limit nor below the lower voltage limit, and spending substantially no time at any intervening voltage between the two states.
In real circuits, however, the input voltage takes a finite amount of time to switch between the two states. Further, when switching between the two states, the input voltage will often exceed the upper limit, i.e., overshoot the voltage, corresponding to the new state, then oscillate, also called ring, around the new voltage before settling down. Clamping circuits, also referred to as termination networks, are designed to minimize the ringing which can seriously degrade circuit performance. A good clamping circuit should dampen ringing and reduce noise so that the signal at the input remains at or near one of the two desired voltage states and switches between those states quickly and cleanly.
Improved clamping performance comes about by supplying or draining current as quickly as possible to/from the network at the input to the circuit being clamped whenever the voltage at the input exceeds or falls below the desired voltage. In order to supply sufficient current, the clamping circuit should have low impedance and a low reflection coefficient in the vicinity of the upper and lower voltages corresponding to the two digital logic states. On the other hand, in order to maximize switching speed between the two logic states, the impedance of the clamping circuit and the reflection coefficient should be very high during switching for the brief time when the input voltage is between the upper and lower digital voltages. Passive clamping circuits which are still widely used, are unable to effectively meet these opposing requirements for high performance applications.
Another requirement for digital circuits is some form of electrostatic discharge (ESD) protection. Generally, separate ESD protection circuits are provided at the input of the circuit to limit the voltage that can be imposed on the circuit at the input terminal even when the circuit is unpowered. It would be desirable if the ESD protection could be incorporated into the clamping circuit. The ability to rapidly drain or source current is important for both clamping and ESD protection. Older designs for clamping circuits that use current limiting resistors do not provide good ESD protection.
As metal oxide semiconductor technology has improved, MOS devices have been constructed with shorter gate lengths, thinner gate oxides and faster response times. As the gate oxide becomes thinner, the device must be powered with a lower voltage power supply to avoid breakdowns and leakage. Lower power supply voltages are also advantageous in reducing power consumption, decreasing heating, and increasing speed through smaller voltage swings. Such lower voltage designs, however, need even more careful control over the input signal to prevent erratic operation due to ringing or other noise at the input. Good ESD protection for such designs is also critical.
A typical prior art five volt system has used a passive clamping circuit in which one diode is placed between the input terminal and Vss and another is placed between the input terminal and Vdd. The diode between the input terminal and Vdd conducts when the voltage at the input terminal rises sufficiently above the upper digital voltage to turn on the diode. Thus, this diode limits the input voltage to about 0.7 volts above the desired maximum input voltage, but permits 0.7 volt ringing around the upper digital voltage. The second diode is positioned between the input terminal and Vss and conducts when the voltage at the input terminal falls one diode drop below the lower digital voltage, usually zero volts. This prevents ringing in excess of about 0.7 volts, but still permits ringing having a magnitude less than the value needed to turn on the passive diode clamp. Passive clamp circuits of this type work in five volt systems because the amplitude of the ringing is relatively small compared to the difference between the upper and lower digital voltages. In lower voltage systems, such as a 3.3 volt system, this 0.7 volt ringing affects the noise tolerance. In voltage systems of 2.5 volts, 1.8 volts, and even 1.2 volts, such ringing is unacceptably large, producing erratic operation in noisy environments. During clamping by a passive diode clamp of this type, the excess signal voltage on the input is pulled towards or clamped to the positive Vdd supply voltage and the lower signal voltage state is pulled towards or clamped to the lower voltage supply Vss or ground. Another concern with the use of diodes in a clamping circuit is that they don't turn off instantly because they have a nonzero storage charge.
In the active clamping circuit of the present invention, improved performance is achieved by activating the clamp as soon as or slightly before the input terminal voltage swings above or below the bounds set by the upper and lower digital voltages. Performance is also improved by driving the input terminal voltage to the upper digital voltage via a connection to Vss when the input voltage is too high, i.e., above the upper voltage which is usually Vdd, and by driving the input terminal voltage to the lower digital voltage via a connection to Vdd when the input terminal voltage is too low, i.e., below the lower digital voltage which is usually Vss. This increases the speed at which the clamping circuit operates as compared to prior art designs which drive excessively low voltages through a conne
Hui David Tinsun
Mashak Benjamin William
Voldman Steven Howard
Williams Robert Russell
Callahan Timothy P.
International Business Machines - Corporation
Nguyen Hai L.
Nock James R.
Ojanen Karuna
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