Active cell crosspoint switch

Details Active cell crosspoint switch Active cell crosspoint switch

2000-10-12

2004-08-03

Horabik, Michael (Department: 2635)

Communications: electrical

Selective

Decoder matrix

C340S014650, C340S014690, C340S002280

Reexamination Certificate

active

06771162

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to integrated circuit crosspoint switches and in particular to a crosspoint switch having switch cells employing active tristate buffers.
2. Description of Related Art
An N×M crosspoint switch, such as disclosed for example in U.S. Pat. No. 5,790,048 issued Aug. 4, 1998 to Hsieh et al, employs an array of pass transistors to selectively route input signals arriving at any of N input ports to any of M output ports.
FIG. 1
illustrates a simplified example 4×4 crosspoint switch
10
as might be implemented in an integrated circuit. Crosspoint switch
10
includes a set of four input signal drivers D
0
-D
3
acting as input ports, a set of four receivers R
0
-R
3
acting as output ports, a switch cell array
12
for selectively providing signal paths between drivers D
0
-D
3
and receivers R
0
-R
3
, and an array controller
14
. Crosspoint array
12
includes four rows and four columns of switch cells
16
. Each of four conductive input lines H
0
-H
3
lines deliver the output of a separate one of drivers D
0
-D
3
to a separate row of switch cells
16
. Each of four conductive output lines V
0
-V
3
lines link a separate column of switch cells
16
to an input of a separate one of receivers R
0
-R
3
. Each switch cell
16
can selectively provide a signal path between one of input lines H
0
-H
3
and one of output lines V
0
-V
3
. A controller
14
writes single bit control data into a memory cell within in each switch cell
16
, and the state of the bit determines whether or not the cell is to provide the signal path. Commands arriving on a control bus
22
from an external source such as a host computer tell controller
14
how to set the states of bits stored in the various switch cells
16
.
When, for example, driver D
0
receives input signal IN(
0
) arriving at one of switch input terminals
18
, it buffers them onto its corresponding input line H
0
. Each one of the four switch cells
16
that are linked to input line H
0
, and which happen to be configured by their stored data bit to provide a signal path, then forwards the signal to one of receivers R
0
-R
3
via its corresponding output line V
0
-V
3
. Each receiver R
0
-R
3
that receives the signal then buffers the signal onto one of four switch output terminals
20
as one of output signals OUT(
0
)-OUT(
3
).
FIG. 2
illustrates a portion of the prior art crosspoint switch
10
of
FIG. 1
in more detail, including driver D
0
, input line H
0
, output lines V
0
-V
3
, the four cells
16
linking input line H
0
to output lines V
0
-V
3
and receivers R
0
-R
3
.
FIG. 2
also shows driver D
0
and receivers R
0
-R
3
of FIG.
1
. Each switch cell
16
includes a pass transistor Q having its source terminal connected to input line H
0
and its drain terminal connected to one of output lines V
0
-V
3
. Each switch cell
16
also includes a memory cell
25
for storing the control bit from controller
14
. Controller
14
of
FIG. 1
uses a control bus
24
to separately write a bit into the memory cell
25
of each switch cell
16
, and that control bit drives the gate of transistor Q. Pass transistor Q of each cell
16
passes signals from input line HO to one of output lines V
0
-V
3
when the bit in memory cell
25
turns the pass transistor on and blocks a signal on line H
0
from passing to that output line when the bit turns the pass transistor off.
Although for simplicity array
12
is illustrated as a 4×4 switch cell array, switch cell arrays of similar design can be made much larger to provide flexible routing paths between much larger numbers of input and output ports. Regardless of the dimensions of crosspoint switch
10
, we would like the crosspoint switch to route signals with as little delay and distortion as possible. However, crosspoint switch
10
can exhibit significant signal path delay and distortion, both of which can increase as we increase the N×M dimensions of array
12
.
Referring to
FIG. 2
, assume that the pass transistor Q of the switch cell
16
linking input line H
0
to output line V
0
is on and that the pass transistors Q of all other switch cells
16
are off. When the input signal IN(
0
) to driver D
0
changes state, the output signal OUT(
0
) produced by driver R
0
will also change state with a time delay that is the sum of the inherent delays of driver D
0
and receiver R
0
and the signal path delay through switch cell array
12
. The signal path delay arises primarily because the output signal produced by driver D
0
on line H
0
must charge or discharge all of the shunt capacitance linked to the input and output lines V
0
and H
0
before it can force receiver R
0
to drive OUT(
0
) to another state. That shunt capacitance includes not only the inherent capacitance of the lines and the input capacitance of the receiver R
0
, it also includes capacitance associated with the pass transistor, Q linked to both input line H
0
and output line V
0
, capacitances associated with the pass transistors Q of the three other switch cells
16
that are also connected to input line H
0
and the three other transistors Q connected to vertical line V
0
.
When we increase the size of the array, for example from 4×4 to 8×8, then each input and output line H
0
and V
0
will now be connected to eight cells, rather than four. Thus driver D
0
will have to charge or discharge the capacitances associated with fifteen transistors rather than seven and input capacitances of up to eight receivers instead of four. Since increasing the size of array
12
increases the capacitance linked to its input and output lines, and since signal delay increases with capacitance, we lengthen the signal path delay when we increase array size.
A driver charges a capacitor at a rate in inverse relation to the product of its capacitance and the series resistance between the driver's voltage source and the capacitor. Thus one way to reduce the signal path delay through array
12
is to increase the size of drivers D
0
-D
3
(i.e., reduce their output resistance) so that they conduct more current when charging and discharging capacitance. This reduces the time the drivers need to charge or discharge the capacitance of array
12
, thereby reducing signal path delay. However since there are practical limits to the size of a driver we can incorporate into an integrated circuit, we would like to provide another way to reduce signal path delay.
We could reduce signal path delay by reducing the capacitance of pass transistors Q by making them smaller. However since smaller pass transistors have higher resistance, the gain in speed resulting from reduced capacitance can be offset by the increased resistance. Therefore while we can attain some delay reduction by optimizing the tradeoff between the capacitance and resistance of pass transistors Q, there are limits to this approach as well. Therefore it would beneficial to provide yet another way to attain further reductions in signal path delay through array
12
.
Signal distortion can be problematic in crosspoint switch
10
. In crosspoint switches implemented using metal oxide semiconductor field effect transistors (MOSFETs), pass transistor Q is typically an n-channel metal oxide semiconductor (nMOS) transistor because nMOS transistors normally have lower capacitance than p-channel metal oxide semiconductor (pMOS) transistors of similar size. However since an nMOS transistor's impedance is not symmetric with respect to the direction of its channel current, transistors Q of
FIG. 2
charge and discharge capacitance at different rates. Signal path delay is therefore a function of whether an input signal IN(
0
)-IN(
3
) is rising or falling. This lack of symmetry results in what is known as “duty cycle” distortion in the OUT(
0
)-OUT(
3
) signals wherein rise and fall times of leading and trailing edges are not symmetric. Since increasing the amount of capacitance that drivers D
0
-D
3
must charge and discharge can increase duty cycle dis

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