Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2002-06-04
2004-09-14
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S067000, C327S057000, C327S055000, C327S552000
Reexamination Certificate
active
06791372
ABSTRACT:
FIELD
Embodiments of the present invention relate to analog circuits, and more particularly, to an active cascode differential latch, useful for discrete-time analog filters.
BACKGROUND
FIG. 1
provides a high-level abstraction of a portion of a computer server or system, where microprocessor
102
resides on board
104
and communicates with memory
106
on board
108
. The communication is by way of striplines on backplane
110
. Backplane
110
is connected to boards
104
and
108
by connectors
112
. Not shown in
FIG. 1
are other memory units and microprocessors, where the various microprocessors and memory units may communicate to one another so as to access or write data and instructions.
Communication of signals over backplane
110
may be modeled by transmission line theory. Often, the signaling is based upon differential signaling, whereby a single bit of information is represented by a differential voltage. For example,
FIG. 2
a
shows drivers
202
and
204
driving transmission lines
206
and
208
, respectively. For differential signaling, drivers
202
and
204
drive their respective transmission lines to complementary voltages. Typical curves for the node voltages at nodes n
1
and n
2
for a bit transition are provided in
FIG. 2
b
, where the bit transition is indicated by a dashed vertical line crossing the time axis. The information content is provided by the difference in the two node voltages.
For short-haul communication, such as for the computer server in
FIG. 1
, the signal-to-noise ratio is relatively large. If the transmission lines are linear, time-invariant systems having a bandwidth significantly greater than that of the transmitted signal, then a relatively simple receiver architecture may be employed to recover the transmitted data. Such a receiver is abstracted by comparator
210
, which provides a logic signal in response to the difference in the two received voltages at ports
212
and
214
.
However, every transmission line has a finite bandwidth, and for signal bandwidths that are comparable to or exceed the transmission line (channel) bandwidth, intersymbol interference may present a problem. Furthermore, actual transmission lines may have dispersion, whereby different spectral portions of a signal travel at different speeds. This may result in pulse spreading, again leading to intersymbol interference. As a practical example, for high data rates such as 10 Gbs (Giga bits per second), the transmission lines used with backplanes or motherboards are such that intersymbol interference is present.
Channel equalization is a method in which a filter is employed at a receiver so as to equalize the channel. The use of digital filters for channel equalization is well known. However, digital filters for such applications require an analog-to-digital converter, which may be costly and difficult to implement at high data rates, and the digital filtering itself may be difficult to implement at high data rates. Consequently, there has been an interest in analog filters for channel equalization. The design of analog filters for channel equalization with high data rates such as 10 Gbs may be challenging. Furthermore, in many high performance applications, the supply voltage is scaling to lower and lower values. This further challenges the circuit designer because of the reduced voltage headroom.
REFERENCES:
patent: 5847598 (1998-12-01), Sone
patent: 6215331 (2001-04-01), Setty et al.
patent: 6288575 (2001-09-01), Forbes
patent: 6373292 (2002-04-01), Choe
patent: 6424181 (2002-07-01), Pogrebnoy
patent: 6449191 (2002-09-01), Lin et al.
Kalson Seth Z.
Nguyen Long
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