Active biasing circuit for an epitaxial region in a fault-tolera

Details Active biasing circuit for an epitaxial region in a fault-tolera Active biasing circuit for an epitaxial region in a fault-tolera

1994-05-23

1995-12-12

Cunningham, Terry

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

327478, 327482, 327530, 327564, 257546, H02J 100, H03K 1760, H01L 2900

Patent

active

054753406

ABSTRACT:
A biasing circuit (30) for an output vertical pnp transistor (10) formed in an integrated circuit and having an outer epitaxial region (20) includes a biasing vertical pnp transistor (33) and a comparator (38). Biasing circuit (30) is electrically connected to the integrated circuit voltage supply and the outer epitaxial region (20) of the output vertical pnp transistor (10) for electrically connecting the outer epitaxial region (20) to the voltage supply when the voltage at an output terminal (23) does not exceed the supply voltage and electrically disconnecting the outer epitaxial region (20) from the voltage supply when the voltage at the output terminal (23) exceeds the supply voltage, whereby improper operation of and damage to the integrated circuit upon the occurrence of an external fault condition is at least minimized.

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