Active bias circuit having wilson and widlar configurations

Details Active bias circuit having wilson and widlar configurations Active bias circuit having wilson and widlar configurations

2001-04-18

2003-02-04

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C323S315000

Reexamination Certificate

active

06515538

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an active bias circuit and more particularly, to an active bias circuit with a combined configuration of the Wilson configuration for current source and the Widlar configuration for current source.
2. Description of the Related Art
FIG. 1
shows a conventional active bias circuit
10
having a combined configuration of the Wilson and Widlar current source configurations As shown in
FIG. 1
, this bias circuit
10
comprises four n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) M
11
, M
12
, M
13
, and M
14
and a resistor R
11
.
Each of the MOSFETs M
11
and M
14
has a so-called diode connection. Thus, the gate and the drain of the MOSFET M
11
are coupled together at the point P
1
and the gate and the drain of the MOSFET
14
are coupled together at the point P
2
. The drain of the MOSFET M
11
is connected to the terminal T
1
by way of the resistor R
11
while the gate of the MOSFET M
11
is connected to the gate of the MOSFET M
13
. The source of the MOSFET M
11
is connected to the drain of the MOSFET M
12
. The gate and the source of the MOSFET M
12
are connected to the gate and the source of the MOSFET M
14
, respectively. The coupled sources of the MOSFETs M
12
and M
14
are connected to the ground. Thus, the MOSFETs M
11
and M
12
located at the input side are connected in cascode.
The drain and the source of the MOSFET M
13
are connected to the terminal T
2
and the drain of the MOSFET M
14
, respectively. The output terminal T
3
of the active bias circuit
10
is connected to the point P
2
at which the gate and the drain of the MOSFET M
14
are coupled together. Thus, the MOSFETs M
13
and M
14
located at the output side also are connected in cascode.
A reference voltage V
1
is applied to the terminal T
1
, thereby generating a reference current I
REF
flowing through the reference resistor R
11
. In other words, the reference current I
REF
is generated by the reference voltage V
1
and the reference resistor R
11
. Since it can be considered that no gate current flows to the gates of the MOSFETs M
11
and M
13
, the reference current I
REF
is equal to the drain current I
D11
of the MOSFET M
11
and to the drain current I
D12
of the MOSFET M
12
(i.e., I
REF
=I
D11
=I
D12
).
A bias voltage V
2
is applied to the terminal T
2
, thereby generating the drain current I
D13
of the MOSFET M
13
. The value of the drain current I
D13
has a specific ratio with respect to that of the reference current I
REF
. Specifically, the value of the drain current I
D13
is a times as much as that of the reference current I
REF
, where a is a positive constant (i.e., I
D13
=aI
REF
). Since it can be considered that no gate current flows to the gates of the MESFETs M
12
and M
14
, the drain current I
D13
is equal to the drain current I
D14
of the MOSFET M
14
(i.e., I
D13
=I
D14
).
The output bias voltage V
OUT
of the conventional bias circuit
10
is generated at the output terminal T
3
. The output bias voltage V
OUT
is equal to the voltage at the connection point P
2
of the gate and the drain of the MOSFET M
14
(i.e., the connection point of the drain of the MOSFET M
14
and the source of the MOSFET M
13
).
A target circuit
20
, to which the output bias voltage V
OUT
is applied from the active bias circuit
10
, includes an n-channel enhancement MOSFET M
15
. The gate of the MOSFET M
15
is connected to the output terminal T
3
of the circuit
10
, receiving the bias voltage V
OUT
of the circuit
10
. The drain of the MOSFET M
15
is connected to the terminal T
4
to which a voltage V
D
is applied. The source of the MOSFET M
15
is connected to the ground. Accordingly, the gate-to-source voltage of the MOSFET M
15
is equal to the output bias voltage V
OUT
, which means that the drain current I
D15
of the MOSFET M
15
of the target circuit
20
increases or decreases according to the output bias voltage V
out
of the bias circuit
10
.
Although the target circuit
20
includes other active elements and passive elements along with the MOSFET M
15
, they are omitted in
FIG. 1
for the sake of simplification.
The conventional active bias circuit
10
of
FIG. 1
operates in the following way.
If the value of the reference resistor R
11
is suitably determined or adjusted according to the value of the reference voltage V
1
(e.g., 2V) applied to the terminal T
1
, the value of the reference current I
REF
flowing through the MOSFET M
11
can be set as desired. Also, due to the reference current I
REF
thus set, the value of the voltage V
P1
at the connection point P
1
(i.e., the connection point of the resistor R
11
and the drain of the MOSFET M
11
) is determined. In this case, the value of the voltage V
p2
at the connection point P
2
(i.e., the output terminal T
3
) is given as the difference of the value of the forward voltage drop V
FM13
of the MOSFET M
13
from that of the bias voltage V
2
applied to the terminal T
2
. Thus, the following equation (1) is established.
V
P2
=K
OUT
=V
2
−V
FM13
  (1)
When the value of the reference voltage V
REF
applied to the terminal T
1
(i.e., the reference current I
REF
) is changed, the values of the drain current I
D13
of the MOSFET M
13
and the forward voltage drop V
FM13
thereof are changed, resulting in change of the output bias voltage V
OUT
. This means that even if the bias voltage V
2
is not changed, the output bias voltage V
OUT
can be changed by changing the reference voltage V
1
.
In the target circuit
20
, the value of the drain current I
D15
of the MOSFET M
15
varies according to the value of the output bias voltage V
OUT
applied to the gate of the MOSFET M
15
. Since the MOSFET M
15
is of the enhancement type, the value of the drain current I
D15
of the MOSFET M
15
can be set as zero (i.e., 0 V) if the value of the output bias voltage V
OUT
is set to be lower than the threshold voltage of the MOSFET M
15
. Thus, the MOSFET M
15
can be cut off.
The operation of the conventional bias circuit
10
shown in
FIG. 1
scarcely fluctuates even if the threshold voltages V
th
of the MOSFETs M
11
, M
12
, M
13
, and M
14
fluctuate due to change of the various parameters in their fabrication process sequence and/or change of the ambient temperature of the circuit
10
during operation. In other words, as long as the parameters of the circuit
10
are kept unchanged, the value of the drain current ID
D15
of the MOSFET M
15
in the target circuit
20
is kept approximately constant in spite of the fluctuation of the threshold voltage and the ambient temperature.
For example, when the absolute values (i.e., amplitude) of the threshold voltages V
th
of the MOSFETs M
11
, M
12
, M
13
, and M
14
decrease, the value of the reference Current I
REF
increases according to the decrease of the threshold voltages V
th
, lowering the voltage V
P1
at the point P
1
On the other hand, according to the increase of the reference current I
REF
, the drain current I
D13
of the MOSFET M
13
increases, which increases the voltage drop generated by the MOSFET M
13
. As a result, the value of the voltage V
P2
at the point P
2
(i.e., the output bias voltage V
OUT
of the circuit
10
) decreases.
On the contrary, when the absolute values (i.e., amplitude) of the threshold voltages V
th
of the MOSFETs M
11
, M
12
, M
13
, and M
14
increase, the value of the reference current I
REF
decreases according to the increase of the threshold voltages V
th
, raising the voltage V
P1
at the point P
1
. On the other hand, according to the decrease of the reference current I
REF
, the drain current I
D13
of the MOSFET M
13
decreases, which decreases the voltage drop generated by the MOSFET M
13
. As a result, the value of the voltage V
P2
at the point P
2
(i.e., the output bias voltage V
OUT
) increases.
With the conventional bias circuit
10
, in the above-described manner, the drain currents I
D13
and I
D14
Of the MOSFETs M
13
and M
14
(and ther

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