Activation of word lines in semiconductor memory device

Details Activation of word lines in semiconductor memory device Activation of word lines in semiconductor memory device

2001-10-15

2003-02-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230010, C365S230060, C365S233100

Reexamination Certificate

active

06525989

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to control of word line activation in a semiconductor memory device.
2. Description of the Related Art
Commonly used semiconductor memory devices include DRAM and SRAM. It is common knowledge that while DRAM offers higher capacity at lower price than SRAM, it requires refresh operations. SRAM, on the other hand, while easier to use due to the lack of a need for refresh operations, is more expensive and has lower capacity than DRAM.
Virtual SRAM (known as VSRAM or PSRAM) is a semiconductor memory device that offers that advantages of both DRAM and SRAM. Virtual SRAM has a memory cell array composed of dynamic memory cells identical to those in DRAM, and also houses a refresh controller that allows refresh operations to be performed internally. Thus, external devices connected to virtual SRAM (such as a CPU) can access (i.e., read or write data) virtual SRAM without being aware of refresh operations. This feature of virtual SRAM is known as “refresh transparency.”
During each cycle in which virtual SRAM is accessed, the word line selected by an address must be activated and deactivated. However, in instances where, for example, the same word line is activated during consecutive cycles, repeated activation and deactivation of the word line during each cycle represents a waste of power. This problem is not limited to virtual SRAM, being common to all semiconductor memory devices in which word lines are repeatedly activated and deactivated in each cycle.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a technique for reducing the power consumption associated with word line activation in semiconductor memory devices.
At least part of the above and the other related objects is attained by a semiconductor memory device. A semiconductor memory device includes: at least one memory cell block of memory cells arranged in a matrix, the memory cell block including a plurality of word lines; an address input section for input of a multiple-bit address that includes a row address for selecting one of the plurality of word lines; a data input/output section for input/output of data corresponding to a memory cell selected by the multiple-bit address; and a word line activation controller for controlling activation of the word lines. The word line activation controller includes: a row address transition detector for detecting whether the row address has changed. When the row address transition detector does not detect a change in the row address during consecutive cycles in which at least one of read and write operations of data for the memory cells are enabled and in which an identical row address is used, the word line activation controller maintains an activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivation thereof until a final cycle of the consecutive cycles.
The semiconductor memory device herein includes a word line activation controller. Where consecutive cycles use addresses that include the same given row address, the word line activation controller maintains in the activated state a word line activated during the initial cycle, without deactivating it until the final cycle in which this same row address is used. The word line activation controller herein obviates the need to repeatedly activate and deactivate word lines in each cycle, thereby reducing the power consumption associated with word line activation.
The advantages of the device herein are particularly notable in cases where data read/write operations on memory cells on an activated word line are performed during two or more cycles among a plurality of cycles that extend from an initial cycle to a final cycle.
In the semiconductor memory device, it is preferable that the address input section is simultaneously supplied with a column address as well as with the row address; and the row address is assigned to a plurality of uppermost bits of the multiple-bit address.
By assigning the row address to the uppermost bits, the row address becomes relatively less likely to change, so that word lines can be more frequently maintained in the activated state, thereby reducing the power consumption associated with word line activation.
The memory cells may be dynamic memory cells that require refreshing within a predetermined period.
The above semiconductor memory device may include a plurality of the memory cell blocks; and the multiple-bit address may include a block address for selecting any one memory cell block from among the plurality of the memory cell blocks. In this arrangement, it is preferable that the word line activation controller is capable of: (i) maintaining the activated state of the word line in a first memory cell block activated during the initial cycle, without deactivation thereof until the final cycle; and, (ii) when at least one of read and write operation of data on a memory cell in a second memory cell block different from the first memory cell block is performed during a cycle among the consecutive cycles after the initial cycle, maintaining an activated state of a word line in the second memory cell block up through the final cycle, without deactivation thereof until the final cycle.
It should be noted that the cycle among the consecutive cycles after the initial cycle may be the final cycle, or a cycle other than the final cycle.
Where there are a plurality of memory cell blocks, the word line activation controller can simultaneously maintain word lines in the activated state in two or more memory cell blocks, thus enabling more frequent data read/write operations to memory cells on activated word lines. This arrangement thus considerably reduces the power consumption associated with word line activation.
The present invention is also directed to a method for controlling activation of word lines in a semiconductor memory device. The semiconductor memory device includes: at least one memory cell block of memory cells arranged in a matrix, the memory cell block including a plurality of word lines; an address input section for input of a multiple-bit address that includes a row address for selecting one of the plurality of word lines; and a data input/output section for input/output of data corresponding to a memory cell selected by the multiple-bit address. When no change in the row address is detected during consecutive cycles in which at least one of read and write operations of data for the memory cells are enabled and in which an identical row address is used, an activated state of a word line activated during an initial cycle of the consecutive cycles is maintained, without deactivation thereof until a final cycle of the consecutive cycles.
The method herein affords advantages and effects similar to those derived from use of the device herein, reducing the power consumption associated with word line activation.
The invention may be embodied in any of a number of forms, for example, a semiconductor memory device; a word line activation control method therefor; a semiconductor memory system comprising a semiconductor memory device and a control device; a method for controlling a semiconductor memory device; or an electronic device comprising a semiconductor memory device.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with the accompanying drawings.


REFERENCES:
patent: 5596543 (1997-01-01), Sakui et al.
patent: 5909407 (1999-06-01), Yamamoto et al.
patent: 11-297067 (1999-10-01), None

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