Acquisition process in a phase-locked-loop by gated means

Details Acquisition process in a phase-locked-loop by gated means Acquisition process in a phase-locked-loop by gated means

1975-07-11

1976-09-28

Kominski, John

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

325421, 328155, 331 1A, 331 14, 331 27, H03B 304

Patent

active

039835065

ABSTRACT:
A phase-locked-loop circuit configuration is described which eliminates the statistical nature of the acquisition process, thereby improving or decreasing the acquisition or lock-up-time of the loop. The circuit configuration is such that given an input signal, that occurs at time T.sub.0, the loop error signal is reduced to a level where the lock-up-time is substantially reduced and predictable to a degree of certainty heretofore unattainable. In addition, by eliminating the statistical nature of the acquisition process, lock-up-time becomes a function of controllable system parameters, such as bandwidth, gain and circuit time constants.

REFERENCES:
patent: 3223943 (1965-12-01), Dumaire et al.
patent: 3328719 (1967-06-01), Lisle et al.
patent: 3805182 (1974-04-01), Melcher
patent: 3882412 (1975-05-01), Apple, Jr.

Affiliated with

Also associated with

Rating

Acquisition process in a phase-locked-loop by gated means does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Acquisition process in a phase-locked-loop by gated means, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Acquisition process in a phase-locked-loop by gated means will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2083407