Static information storage and retrieval – Analog storage systems
Reexamination Certificate
2001-12-20
2003-12-23
Elms, Richard (Department: 2824)
Static information storage and retrieval
Analog storage systems
C365S191000, C365S194000, C365S200000, C365S231000, C327S033000, C327S091000, C327S094000
Reexamination Certificate
active
06667894
ABSTRACT:
FIELD OF THE INVENTION
The invention concerns an acquisition process first sampling analog signals, comprising high-speed analog signal sampling, storing signal samples in a matrix of memory cells, and re-reading the samples from the cells at low speed, and an acquisition system to implement such a process.
BACKGROUND
Known sampling systems have the particular disadvantage of too high a noise level and, as a consequence, relatively low useful signal-to-noise ratios.
SUMMARY OF THE INVENTION
The purpose of the invention is to provide an acquisition system for analog signal sampling which eliminates the above-mentioned disadvantages.
To achieve that goal, the acquisition system according to the invention includes two identical memory devices are provided in each memory cell, where one sample of an analog signal is stored in one memory device and a sample of that signal more or less out of phase is stored in the other device.
According to one characteristic of the invention, the out-of-phase signal is delayed in relation to the in-phase signal before being applied to the corresponding write bus channel for a predetermined period of time, advantageously equal to one half-period of the sampling signal.
The acquisition system for analog signal sampling according to the invention, comprises a matrix of analog memory cells arranged in a plurality of rows and columns, each cell being connected to a write bus and a read bus, and having two inputs for activation control signals received from a clock signal, a horizontal shift register and a vertical register, designed to deliver activation control signals to the cells for the writing and reading functions of the cells, wherein the write bus and the read bus each have two channels, that one of the two write bus channels receives the analog signal to be sampled more or less out of phase in relation to the other channel, and that each memory cell includes two memory devices, each of which is connected to one of the two write bus channels and read bus channels.
REFERENCES:
patent: 4271488 (1981-06-01), Saxe
patent: 5526286 (1996-06-01), Sauerwein et al.
patent: 5526301 (1996-06-01), Saxe
patent: 5805492 (1998-09-01), Gerna et al.
patent: 6091619 (2000-07-01), Kogan
patent: 11-283396 (1999-10-01), None
Arnoux Daniel
Genter Claude
Pion Francisque
Arnoux Chauvin
Elms Richard
Leydig , Voit & Mayer, Ltd.
Luu Pho
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