Acquisition delay circuit for a PLL reference oscillator

Details Acquisition delay circuit for a PLL reference oscillator Acquisition delay circuit for a PLL reference oscillator

1979-10-04

1981-05-12

Ng, Jin F.

Telecommunications

Receiver or analog modulated signal frequency converter

Signal selection based on frequency

455183, 455173, 455192, 3581951, H03B 306

Patent

active

042676029

ABSTRACT:
A delay circuit for enhancing acquisition of a synthesizer PLL subsequent to change in the synthesizer's frequency of operation or a change in the source of tuning voltage applied to a voltage-controllable reference oscillator. A control circuit determines whether the reference oscillator operates in a crystal-controlled or in a voltage-controlled mode. The delay circuit includes a monostable having an output coupled to the control circuit and a trigger input coupled to both an ENTER CHANNEL indicator and a pulse generator. The monostable is triggered, thereby assuring temporary crystal-controlled operation of the reference oscillator, in response to an ENTER CHANNEL indicator or to an output from a pulse generator. The pulse generator is responsive to a change in the source of reference oscillator tuning control voltage from, for example, a manually variable fine tuning potentiometer to an AFC control circuit.

REFERENCES:
patent: 3440544 (1969-04-01), Pampel
patent: 3675146 (1972-07-01), Langham
patent: 3764916 (1973-10-01), Merrell
patent: 3949158 (1976-05-01), Rzeszewski
patent: 4009438 (1977-02-01), Grohmann
patent: 4128849 (1978-12-01), Rhee
patent: 4208741 (1980-08-01), Brun et al.

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