Accurate wafer patterning method for mass production

Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask

Reexamination Certificate

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C438S692000, C438S693000, C438S462000, C216S089000, C216S090000

Reexamination Certificate

active

06586143

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of automatically compensating for alignment of a wafer stepper in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of integrated circuit devices, multiple layers of conductors and insulators are deposited and patterned to construct the integrated circuit. It is critical to align each subsequent layer with the previous layer with precision. As design rules scale to smaller dimensions, the overlay budget; i.e., the relative displacement between a patterned layer and the previously defined layer, is expected to be reduced. For example, the overlay budget for 0.25 &mgr;m feature size is about 90 nm; for 0.18 &mgr;m feature size, about 70 nm; and for 0.13 &mgr;m feature size, the overlay budget is expected to be 50 nm. The shrinking overlay budget is one of the most difficult obstacles in lithography where level-to-level alignment is concerned, especially in complex structures of metal and contacts or vias.
The overlay tolerance can shrink even further by the use of zero enclosure or borderless design rules, which are gaining popularity among circuit designers due to significant savings in the device area. This means that an accurate mechanism of stepper alignment is needed.
The alignment accuracy of the patterning machine is of particular importance to deliver the overlay budget as stipulated. Today's patterning machines rely very much upon the equipments' capability, including the stage accuracy for wafer and reticle. Alignment is typically accomplished by using alignment marks. A wafer stepper tool uses the alignment marks on a wafer as a reference point for adjusting a reticle over the wafer. The reticle contains the pattern to be generated within the layer. The morphology of the alignment mark is important in determining the quality of alignment. The impact of process variations on the alignment mark implies that robust and extremely tightly controlled variables are required in the process of achieving a very small overlay budget. As far as mass production is concerned, where more than one machine is used for patterning, machine matching will also be required for acceptable overlay performance.
Removal of correctable overlay errors is often achieved through adjustments to stepper parameters. The magnitudes of these process corrections are determined typically by exposing test or pilot wafers
12
and measuring the overlay using the overlay machine,
14
, as elaborated in FIG.
1
. Compensations for stepper alignment are determined
16
and then implemented. In this way, the amount of rework can be reduced significantly as the test wafer is used as a dummy to test the alignment before proceeding with the rest of the wafers
18
.
The test wafer procedure normally is conducted in the research and development mode as well as in production when a new device is introduced. This procedure is followed through until the process is stable. However, in many cases, when there is a shift in process conditions, the stepper compensations will be shifted also. As such, misalignment is detected and the test wafer procedure has to be followed through once more.
In a foundry where many types of devices are manufactured, a very thorough data base has to be kept in order to maintain the stepper compensation scheme. This procedure and scheme can be very time consuming and expensive.
U.S. Pat. No. 5,503,962 Caldwell discloses an alignment mark and CMP process in which alignment marks are formed in oxide layers using the same process as for contact and via formation. U.S. Pat. Nos. 5,627,624 and 5,329,334 Yim et al disclose test reticles containing various types and sizes of alignment marks and an alignment mark optimization method. Co-pending U.S. Pat. No. 6,184,104 to J. B. Tan et al, filed on Sep. 10, 1998, teaches the generation of alignment marks only at the oxide layers for use with CMP processes.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of increasing the accuracy of patterning machines to pattern wafers with minimum overlay.
Another object of the invention is to provide a method of automatically checking the position of alignment marks in the manufacture of integrated circuits.
A further object of the invention is to provide a method of automatically checking the position of alignment marks so that the stepper can compensate for correctable alignment error.
Yet another object is to provide a method of automatically checking the position of alignment marks after a chemical mechanical polishing (CMP) process and providing feedback if a deviation occurs.
A still further object of the invention is to provide a method of checking the position of alignment marks after a chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking in the fabrication of integrated circuits.
In accordance with the objects of this invention a method for checking the position of alignment marks after a chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking is achieved. A wafer is provided having an alignment mark thereon for the purpose of aligning a reticle in the wafer stepper. The wafer is polished by CMP. Thereafter, alignment mark positioning is checked for deviation from a normal vectorial position of the alignment mark whereby information about the deviation is fed back to the wafer stepper and wherein the wafer stepper automatically compensates for correctable alignment error based on the deviation information.


REFERENCES:
patent: 5329334 (1994-07-01), Yim et al.
patent: 5503962 (1996-04-01), Caldwell
patent: 5627624 (1997-05-01), Yim et al.
patent: 6074950 (2000-06-01), Wei
“Advanced Process Control: Soon to be a Must”, Semiconductor International; (7-991); vol. 22; No. 8; Baliga; pp. 76-86.*
“Characterization and Optimization of Overlay Target Design for Shallow Trench Isolation (STI) Process”; Proc. of SPIE; 1999; vol. 3677, pt. 1-2; pp 217-218; Hsu et al.

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