Accurate ultra-low current generator

Details Accurate ultra-low current generator Accurate ultra-low current generator

2001-10-19

2003-12-02

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S313000, C363S073000

Reexamination Certificate

active

06657420

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to and apparatus and method for generating low currents. More particularly, the present invention is related to current generators that accurately generate low currents using switched capacitor techniques.
BACKGROUND OF THE INVENTION
An accurate current can be generated with an operational amplifier that is arranged in a feedback loop. The operational amplifier (op-amp) is arranged to force a known reference voltage across a known resistor value. The resistor and op-amp are arranged to convert the reference voltage to current. An example current generator circuit (
400
) that uses an operational amplifier is illustrated in FIG.
4
.
As shown in
FIG. 4
, current generator circuit (
400
) includes an N-type field effect transistor (FET MSF), three resistors (R
41
-R
43
), and an operational amplifier (AMP
40
). FET MSF includes a gate that is connected to a control node, a drain that is connected to an output node (OUT), and a source that is connected to a feedback node. Resistor R
41
is connected between the feedback node and ground. Resistors R
42
and R
43
are series connected between a voltage reference terminal (VREF) and ground. Amplifier AMP
40
includes a non-inverting input that is connected to a common node between resistors R
42
and R
43
, an inverting input that is connected to the feedback node, and an output that is coupled to the control node.
In operation, a reference voltage (VREF) is applied to the current generator circuit (
400
). Resistors R
42
and R
43
operate as a resistor divider that provides a second reference voltage (VR
2
) in response to the reference voltage (VREF). FET MSF receives a control voltage (VCTL) from the output of amplifier AMP
40
and produces an output current (IOUT). The output current (IOUT) flows through resistor R
41
, which produces a feedback voltage (VFB). Amplifier AMP
40
provides the control voltage (VCTL) in response to a comparison between the second reference voltage (VR
2
) and the feedback voltage (VFB). Amplifier AMP
40
provides control of FET MSF such that output current IOUT is determined by the second reference voltage (VR
2
) divided by the resistance of R
41
.
SUMMARY OF THE INVENTION
The present invention is directed to a method and apparatus for accurately generating low currents using switched capacitor techniques. The current generator includes a reference voltage generator that provides a reference signal to a switched capacitor integrator. In one example, the reference circuit includes a switched capacitor divider. The switched capacitor integrator circuit produces a voltage ramp in response to the reference signal and other timing signals. The rate of the voltage ramp is proportional to the ratio of capacitors in the switched capacitor integrator and a clock frequency that is associated with the timing signals. A feedback circuit impresses the voltage ramp across an output capacitor circuit that has a very low capacitance value. The capacitor is arranged to differentiate the voltage ramp to produce an accurate low current. The switched capacitor design is suitable for integration in a monolithic integrated circuit. The integrator and the feedback stage are periodically reset.


REFERENCES:
patent: 5949666 (1999-09-01), Daniele et al.
patent: 6177787 (2001-01-01), Hobrecht
patent: 6329803 (2001-12-01), Hitchcock

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