Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-01-18
2001-12-04
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S273000
Reexamination Certificate
active
06326825
ABSTRACT:
BACKGROUND OF THE INVENTION
A primary concern among users of modern electronic devices is power consumption. For example, the length of time that a user may operate a particular portable electronic product before recharging the associated battery is generally a major purchase consideration for most consumers. Consequently, a major goal of most electronics designers is to reduce the power consumption of their product designs.
Toward this end, many electronic component manufacturers provide integrated circuits (ICs) with a “low-power” mode in addition to their normal “high-power” state. (Other designations for lower power states exist, such as “standby” or “sleep” mode. Additionally, many ICs implement several different low-power levels, each with its own level of functionality and power consumption.) The electronics designers incorporate these ICs into their product designs, utilizing the low-power mode of the ICs prudently so that the products consume the least amount of power possible while still providing the functionality and performance that the user expects.
In general, placing an IC into a low-power state results in the primary functionality of the IC being disabled. During low-power mode, many circuits internal to the IC, including high-frequency clock signals and input/output (I/O) drivers, are essentially turned off, thereby dissipating very little electrical power. Once it is determined that the IC needs to perform a function that requires low-power mode to be terminated, a “wake up” signal is used to end low-power mode, thus bringing the circuit to a fully functional, high-power state.
One common example of a wake-up signal is the output of a time delay circuit that is triggered at the time a portion of the IC is placed in low-power mode. After a desired length of time that a portion of the IC has been in low-power mode, the time delay circuit generates a wake-up signal that returns the low-power portion of the IC to its normal high-power state. A time delay circuit is typically used in this role when a portion of IC circuitry in low-power state must be awakened periodically to perform a specific function before returning to low-power mode. Often, such a time delay circuit is implemented, as shown in
FIG. 1
, by a precision resistor R
1
in series with a precision capacitor C
1
, configured as a low-pass filter. External precision components are normally used since the accuracy of the time delay circuit is somewhat important for many electronics applications. The time constant of this circuit, along with the threshold voltage of the IC input acting as the wake-up signal input, determines the time delay (the delay between voltage V
start
going high and voltage V
delay
going high) until the low-power portion of the IC is awakened. Unfortunately, such a solution requires relatively expensive external components, valuable space on the associated circuit board to house the components, and an IC package pin dedicated to the wake-up signal.
To eliminate the need for an extra IC package pin, expensive external components, and additional circuit board space for the wake-up function, the circuit that generates the wake-up signal could be implemented on the low-power-capable IC. For example, an internal timer circuit driven by a highly accurate onboard crystal or resonator oscillator that generates a stable accurate clock signal may be used for such a purpose. However, such an accurate oscillator generally consumes a few tens to several hundreds of milliamps of current, thus making the accurate oscillator a high-power circuit that should be turned off in low-power mode. Additionally, the superb accuracy of such oscillators is simply not necessary when applied to a wake-up time delay circuit. Other types of oscillator circuits, such as ring oscillators or relaxation oscillators, may be utilized to drive the time delay circuit. Unfortunately, such low-power oscillators are rather unstable and inaccurate, their operating frequency varying by as much as a factor of two- or three-to-one over changes in IC process, supply voltage, and operating temperature. For the majority of IC applications, such frequency variations of inaccurate oscillators are not acceptable for a wake-up time delay circuit.
Therefore, it would be advantageous to implement a time delay circuit utilizing an inaccurate oscillator that generates an accurate time delay signal.
SUMMARY OF THE INVENTION
Specific embodiments according to the present invention, to be described herein, provide a useful way for an inaccurate oscillator to be utilized as part of an accurate time delay circuit. An accurate clock signal, possibly generated by a high-frequency oscillator, serves to calibrate the inaccurate oscillator prior to the initiation of a desired time delay, during which the accurate clock signal will be unavailable. When the desired time delay is to commence, the calibration information previously gathered is utilized to generate an accurate delay using the inaccurate oscillator.
In one embodiment of the invention, a time delay system uses an accurate high-frequency clock signal as an input signal. The time delay circuit has an inaccurate oscillator that generates an inaccurate clock signal with a frequency that is lower than the frequency for the accurate clock signal. A first clock counter circuit counts the number of cycles of the accurate clock signal that occur during a known portion of the inaccurate clock signal. A digital processing unit takes the number of cycles counted by the first clock counter circuit, along with the number of periods in the predetermined portion of the inaccurate clock signal, the period of the accurate clock signal, and a desired time delay, to calculate a desired number of inaccurate clock signal cycles representing the desired time delay. An second clock counter circuit then counts inaccurate clock signal cycles until the desired number is reached, at which point the second clock counter circuit generates a signal indicating that the desired time delay has elapsed.
A second embodiment of the invention involves the use of an inaccurate oscillator that generates an inaccurate clock signal with a frequency that is higher than the frequency of an accurate clock signal. Given these conditions, the first clock counter circuit counts the number of cycles of the inaccurate clock signal that occur during a known portion of the accurate clock signal. A digital processing unit then takes the number of cycles counted by the first clock counter circuit, along with the number of periods in the predetermined portion of the accurate oscillator signal, the period of the accurate clock signal, and a desired time delay, to calculate a desired number of inaccurate clock signal cycles representing the desired time delay. As in the previous embodiment, a second clock counter circuit then counts inaccurate clock signal cycles until the desired number is reached, at which point a signal indicating that the desired time delay has elapsed is generated.
In another embodiment, a method of implementing a time delay begins with counting a number of cycles of an accurate clock signal that occur during a predetermined portion of an inaccurate clock signal, assuming the inaccurate clock signal has a frequency that is lower than the frequency of the accurate clock signal. A desired number of cycles of the accurate clock signal corresponding to a desired time delay is then calculated using the number of cycles from the counting step, the number of periods in the predetermined portion of the inaccurate oscillator signal, and the period of the accurate clock signal. The desired number of cycles of the inaccurate oscillator signal are then counted, and the fact that the desired time delay has elapsed is indicated.
Another method embodiment is employed when the frequency of the inaccurate clock signal is higher than that of the accurate clock signal. First, the number of cycles of the inaccurate clock signal that occur during a predetermined portion of the inaccurate clock signal are counted. A desired number of cycle
Agilent Technologie,s Inc.
Nu Ton My-Trang
Way Kyle J.
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