Accurate parasitics estimation for hierarchical customized...

Details Accurate parasitics estimation for hierarchical customized... Accurate parasitics estimation for hierarchical customized...

2011-03-22

2011-03-22

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S125000, C716S126000

Reexamination Certificate

active

07913216

ABSTRACT:
Disclosed is a method of estimating interconnect wire parasitics in integrated circuits which includes obtaining a circuit layout having circuit components placed thereon including source input/output (I/O) pins and sink I/O pins, the circuit layout having a circuit hierarchy, bubbling up of the I/O pins until all I/O pins are on a same level of the circuit hierarchy, and then estimating interconnect segments to be employed in interconnecting at least some circuit components of the placed circuit components of the circuit layout. Also disclosed is a circuit design system and program storage device.

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Shi et al, “A Fast Hierarchical Algorithm for Three-Dimensional Capacitance Extraction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, No. 3, pp. 330-336, Mar. 2002.

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