Accurate, high drive, zero offset voltage buffer

Details Accurate, high drive, zero offset voltage buffer Accurate, high drive, zero offset voltage buffer

2005-02-01

2005-02-01

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including field effect transistor

C330S300000

Reexamination Certificate

active

06850116

ABSTRACT:
A low offset voltage buffer which comprises a first, second, third and fourth MOS device, each comprising a gate, a source and a drain; a current source coupled to the drains of the first and second MOS devices; a current sink coupled to the sources of the third and fourth MOS devices; an input coupled to the gate of the third MOS device and an output coupled to the source of the first MOS device. The source of the first MOS device is coupled to the drain of the third MOS device and the source of the second MOS device is coupled to the drain of the fourth MOS device. The voltage buffer can also be implemented in both NMOS and PMOS devices.

REFERENCES:
patent: 5023567 (1991-06-01), O'Shaughnessy et al.
patent: 5070306 (1991-12-01), Okamoto
patent: 5406219 (1995-04-01), Lou
patent: 5821814 (1998-10-01), Katayama et al.

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