Accurate digital fault tolerant clock

Details Accurate digital fault tolerant clock Accurate digital fault tolerant clock

1994-08-12

1996-09-17

Beausoliel, Jr., Robert W.

Excavating

371 36, G11B 2700

Patent

active

055576230

ABSTRACT:
This invention relates to fault-tolerant real-time clock capable of withstanding n-faults, including Byzantine faults. In particular, the instant invention produces redundant clock signals which have low skew with respect to each other, operate with extremely high accuracy, and can be constructed without use of analog electric components, with the exception of oscillators. The present fault tolerant clock is composed of three types of electrical subcircuits coupled together: oscillators/counters, sequential edge voters, and regular voters. Each of these subcircuits can be duplicated and coupled appropriately as needed to form a clock mechanism tolerant of any number of faults in the clock circuitry while maintaining an extremely precise timing mechanism suitable for accurately integrating and differentiating signals with respect to time.

REFERENCES:
patent: 4239982 (1980-12-01), Smith et al.
patent: 4864574 (1989-09-01), Pritt
patent: 4972414 (1990-11-01), Borkenhagen et al.
patent: 4979191 (1990-12-01), Bond et al.
patent: 4984241 (1991-01-01), Truong
patent: 5109506 (1992-04-01), Begun
"Clock failure recovery by automatic reinitialization and subsequent system restart" vol. 32, No. 3B, Aug. 1989.
B. H. Tulpule et al., "Achieving Fault Tolerance in Multichannel Control Systems", Oct. 14, 1991, Proceedings IEEE/AIAA 10th Digital Avionics Systems Conference, Los Angeles, California,, pp. 275-280.

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