Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2002-07-02
2004-08-31
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S108000, C702S110000, C702S117000, C702S120000, C365S145000, C714S718000
Reexamination Certificate
active
06785629
ABSTRACT:
BACKGROUND
A ferroelectric random access memory (FeRAM) generally includes an array of FeRAM cells where each FeRAM cell contains at least one ferroelectric capacitor. Each ferroelectric capacitor contains a ferroelectric material sandwiched between conductive plates. To store a data bit in a FeRAM cell, a write operation applies write voltages to the plates of the ferroelectric capacitor in the FeRAM cell to polarize the ferroelectric material in a direction associated with the data bit being written. A persistent polarization remains in the ferroelectric material after the write voltages are removed and thus provides non-volatile storage of the stored data bit.
A conventional read operation for a FeRAM determines the data bit stored in a FeRAM cell by connecting one plate of a ferroelectric capacitor to a bit line and raising the other plate to a read voltage. If the persistent polarization in the ferroelectric capacitor is in a direction corresponding to the read voltage, the read voltage causes a relatively small current through the ferroelectric capacitor, resulting in a small charge and voltage change on the bit line. If the persistent polarization initially opposes the read voltage, the read voltage flips the direction of the persistent polarization, discharging the plates and resulting in a relatively large charge and voltage increase on the bit line. A sense amplifier can determine the stored value from the resulting bit line current or voltage.
Development, manufacture, and use of an integrated circuit such as FeRAM often require testing that determines the characteristics of the integrated circuit and determines whether the integrated circuit is functioning properly. One important test for a FeRAM is measurement of the charge delivered to bit lines when reading memory cells. Generally, the bit line charge or voltage that results from reading a FeRAM cell varies not only according to the value stored in the FeRAM cell but also according to the performance of the particular FeRAM cell being read. The distribution of delivered charge can be critical to identifying defective FeRAM cells that do not provide the proper charge and to selecting operating parameters that eliminate or minimize errors when reading or writing data.
A charge distribution measurement generally tests each FeRAM cell and must measure the amount of charge read out of the FeRAM cell for each data value. Measuring the readout charge commonly requires using a sense amplifier to compare a bit line signal read from the FeRAM cell to up to 100 or more different reference levels. Each of the comparisons generates a binary signal indicating the results of the comparison. The binary comparison result signals can be output using the same data path used for read operations. Comparing the bit line voltage read from a single FeRAM cell storing a data value “0” or “1” against 100 reference levels generates 100 bits of test data. Accordingly, the amount of test data generate during a distribution measurement for all cells in an FeRAM requires a relatively long time to output using the normal I/O cycle time. Charge distribution measurement for data values “0” and “1” in a 4-Megabit FeRAM, for example, can generate more than 8×10
8
bits of test data, which may require several minutes to output. Further, the amount of test data and output time increase with memory storage capacity.
The large volume of data output from a FeRAM for a charge distribution measurement may require too much time for an efficient testing during integrated circuit manufacture. Processing the large amount of data to construct bit line voltage distributions can also create a bottleneck in a fabrication process. The amount of data can be reduce by testing only a sampling of the FeRAM cells in a FeRAM but sampling may fail to uncover some defective FeRAM cells.
In view of the current limitation of methods for measuring charge distributions of FeRAMs, structures and methods that reduce the data flow and processing burdens for measurement of charge distributions are sought. The reduced data will ideally indicate the charge distribution information but also indicate the accuracy or the amount of noise in the charge distribution information. Further, the reducing the amount of test data while retaining accuracy information would be best accomplished without requiring large or complex on-chip circuits.
SUMMARY
In accordance with an aspect of the invention, an on-chip circuit measures the distribution of bit line voltages or charge resulting from reading FeRAM cells and compresses distribution data to reduce the amount of output data and the time required for output of the distribution data. The measurement of a bit line voltage typically involves operating a sense amplifier to compare a bit line voltage to a series of reference voltages. Instead of directly outputting result signals from the sense amplifier, a compression circuit processes the result signals to generate values indicating lower and upper limits of a range of reference voltages in which noise can cause sensing operations to provide inconsistent results. A small reference voltage range indicates that bit line voltage was accurately measured.
One embodiment of a compression circuit includes a counter and a set of registers or other storage elements connected to the counter. The counter is synchronized with changes in a reference signal input to a sense amplifier and to the series of comparisons so that the count from the counter indicates a current reference voltage that sense amplifiers are comparing to bit line voltages. Each of the storage elements corresponds to a bit line being tested and operates to store the count from the counter when the binary result values for the comparisons have a particular value. The stored value at the end of the bit line voltage measurement is a count value indicating the reference voltage (or count) that the comparisons first or last indicated as greater than the bit line voltage. To quantify noise in the comparisons, multiple count values for each bit line can be stored using different triggering conditions so that the count values indicate when more than one transition occurs in the results stream.
In one embodiment of the invention, instead of directly connecting the outputs of the sense amplifiers to enable or disable the storage elements, the output signals from the sense amplifiers control the gates of drive devices (e.g., pull-down or pull-up transistors) of a bus connected to provide enable signals to the storage elements. A precharge circuit charges the bus to a state that enables the storage devices to replace a stored value with a fresh value from the counter. Whenever a particular sense amplifier activates its associated drive device, the drive device pulls the enable signal for the corresponding storage element to a state that disables changing the stored value in the storage element. Changing the precharging scheme for the global I/O bus can provide obtain upper and lower limits for the voltage range in which noise can cause inaccurate sensing. One limit is obtained by only precharging the global I/O bus before the series of sensing operations that measure a bit line voltage. With this precharging scheme, the storage element retains the count corresponding to reference voltage just before the first sensing operation that causes the corresponding drive circuit to pull the enable signal to the disabling state. The other limit is obtain by precharging the global I/O line before each sensing operation, which causes the storage element to retain the count corresponding to the last sensing operation that failed to pull the global I/O line to the disabling state.
Another embodiment of the invention is a method for testing an integrated circuit containing FeRAM cells. The test method includes: performing sensing operations that respectively compare a series of reference voltages to a bit line voltage; generating a first data value identifying a first limit for a range of the reference voltages in which the sensing operations provided incons
McAdams Hugh P.
Rickes Juergen T.
Agilent Technologie,s Inc.
Hoff Marc S.
Tsai Carol S W.
LandOfFree
Accuracy determination in bit line voltage measurements does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Accuracy determination in bit line voltage measurements, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Accuracy determination in bit line voltage measurements will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3276585