Accumulator with programmable full-scale range

Details Accumulator with programmable full-scale range Accumulator with programmable full-scale range

2001-06-12

2004-08-17

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06779010

ABSTRACT:

RELATED APPLICATIONS
The present application is related to concurrently filed non-provisional applications:
(i) by A. W. Hietala entitled
Fractional
-
N Modulation with Analog IQ Interface;
(ii) by B. T. Hunt and S. R. Humphreys entitled
Dual
-
Modulus Prescaler;
(iii) by S. R. Humphreys and A. W. Hietala entitled
Fractional
-
N Synthesizer with Improved Noise Performance
; and
(iv) by B. T. Hunt and S. R. Humphreys entitled
True Single
-
Phase Flip
-
Flop
, which non-provisional applications are assigned to the assignee of the present invention, and are hereby incorporated in the present application as if set forth in their entirety herein.
FIELD OF THE INVENTION
The present invention relates to digital electronic circuitry. More particularly, the present invention relates to digital accumulators. Still more particularly, the present invention relates to digital accumulators for use in fractional-N (F-N) synthesizers.
BACKGROUND OF THE INVENTION
Phase-locked loop (PLL) frequency synthesis is a well-known technique for generating a variety of signals of predetermined frequency in many applications, e.g., digital radiotelephone systems. Briefly, the output of a voltage-controlled oscillator (VCO) is coupled to a frequency divider for providing one input to a phase detector. Another input to the phase detector is a reference signal from a fixed frequency source having high stability over a range of operating conditions. Differences in phase determined by the phase detector (typically reflected as charge pulses) are then filtered and applied to the VCO to control changes to the frequency of the VCO of such magnitude and sign as to reduce the detected phase difference.
Fractional-N (F-N) synthesizers based on the above-described PLL frequency synthesis techniques have been in favor for some time because, inter alia, they provide for non-integer division of the VCO output, thereby providing greater flexibility in choosing the VCO output frequency, and allowing the use of higher frequency reference sources with the concomitant potential for wider bandwidth and faster loop locking times. Other background aspects of RF synthesizers (and, in particular, F-N synthesizers), and their implementation and use, are presented in B. Razavi,
RF Microelectronics
, Prentice-Hall PTR, 1998, especially pp. 269-297, and in incorporated related patent application (i-v) cited above.
FIG. 1
shows a prior art F-N synthesizer arrangement in which a reference signal, e.g., from stable frequency source is applied on input
135
as one input to a phase detector
130
. The other input to phase detector
130
is a frequency divided output from programmable divider
120
on path
125
. Divider
120
, in turn, receives an input from the output of VCO
100
, which output is the frequency-controlled output of the synthesizer of FIG.
1
. The integer part of the division ratio is applied on line
175
and input reflecting the fractional part of the division ratio is applied on line
155
. More specifically, fractional sequence generator
150
responds to an applied fractional divisor input on lead
170
to provide a time-variable sequence of integer values, which, when applied through adder
160
allow a variable divisor to be realized in divider
120
. Typically, fractional sequence generator
150
is clocked by the output of divider
120
, and a new instantaneous divisor value is provided for each cycle of that clock. The overall effect of the application of this time-varying integer divisor in divider
120
is to apply a divisor to divider
120
that has an average value equal to the sum of the integer and fractional inputs on
175
and
170
, respectively.
In operation, the prior art synthesizer of
FIG. 1
controls the frequency of VCO
100
in response to varying integer divisors by applying a time-variable frequency divided version of the output from VCO
100
to phase detector
130
. In comparing phase information for the frequency divided input from divider
120
with the reference signal on input
135
, phase detector
130
develops an error signal that is smoothed in low pass loop filter
140
and applied to VCO
100
in such manner as to reduce the phase error between the reference signal and the frequency divided signal from divider
120
. In doing so, the output from VCO
100
tracks the desired frequency variations specified by fractional inputs on input
170
.
Overall, if the desired fractional output of the divider is represented as a numerator, C, and a denominator, D, then the output sequence, SEQ, from sequence generator
150
in
FIG. 1
is given by
avg
(
SEQ
)=
C/D,
where avg) represents an averaging operation. When SEQ is added to the integer value appearing on
175
in
FIG. 1
, the instantaneous value of the divisor is given by
N[i]=N
int
+SEQ[i],
where SEQ[i] is the instantaneous value of the sequence and N
int
is the integer portion of the divisor presented on
175
. Thus, the average of total divisor value N is given by
avg
(
N
)=
N
int
+avg
(
SEQ
)=
N
int
+C/D.
The fractional-n PLL then locks the VCO
100
in
FIG. 1
to the frequency
F
vco
=F
ref
.(
N
int
+C/D
),
which has a resolution or step size given by
F
step
=F
ref
/D.
FIG. 2
shows a prior art fractional sequence generator
200
based generally on aspects of a F-N synthesizer circuit arrangement shown in U.S. Pat. No. 4,609,881 issued Sep. 2, 1986 to J. N. Wells, which patent is hereby incorporated by reference as if set forth in its entirety herein. The sequence generator of
FIG. 2
includes an accumulator structure
210
having a plurality of accumulators—each comprising an n-bit bank of D flip-flops (an n-bit register),
230
-
i
, i=1, 2, and 3 and a corresponding n-bit adder
225
-
i
, i=1, 2, and 3. Adder
225
-1 receives a fractional divisor value f (the least significant bits of a divisor of the form N.ƒ, where N is an integer) on the C input path
215
during a current clock cycle of the output of divider
120
. Clock signals corresponding to the output of divider
120
are provided as inputs on F
v
input
220
. The value f on input
215
is added to the previous contents of n-bit register
230
-1 and the result is stored in register
230
-1. In addition, when register
230
-1 overflows (provides a carry-out indication on recombination output CO
1
), that signal is immediately applied to adder
240
at an input labeled +1. The set of recombination paths is conveniently referred to as recombination network
205
.
As further shown in
FIG. 2
, the sum stored in register
230
-1 is also provided as an input to adder
225
-2, where it is combined with the prior contents of register
230
-2 during the following clock cycle. Again, the result of the addition is stored back in register
230
-2 and a carry indication is provided on recombination path CO
2
when overflow of adder
230
-2 occurs is applied to an input to adder
240
labeled +1. In addition, the same overflow signal on CO
2
is applied to a −1 input to adder
240
after a delay of one additional clock cycle. Such additional delay of one clock cycle is provided by delay flip-flop
250
.
In similar fashion, adder
230
-3 receives the result of the addition performed at adder
230
-2 and adds it to the prior contents of register
230
-3. Again, the result of the addition is stored back to register
230
-3, and, when a carry-out occurs from adder
225
-3, recombination path CO
3
supplies the carry-out signal to a +1 input to adder
240
. In addition, the CO
3
recombination path provides the carry-out indication to delay flip-flop
260
, thereby providing the carry out signal to a −2 input to adder
240
after an additional clock cycle. Further, the delayed CO
3
signal on the output of flip-flop
260
is also provided as an input to delay flip-flop
270
where it provides the carry-out signal to a +1 input to adder
240
after yet another clock cycle (a total delay of two clock cycles).
Each of the carry-out signa

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