Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2005-11-08
2005-11-08
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C326S041000, C712S221000, C716S030000
Reexamination Certificate
active
06963966
ABSTRACT:
Methods and structures for efficiently implementing an accumulator-based load-store CPU architecture in a programmable logic device (PLD). The PLD includes programmable logic blocks, each logic block including function generators that can be optionally programmed to function as lookup tables or as RAM blocks. Each element of the CPU is implemented using these logic blocks, including an instruction register, an accumulator pointer, a register file, and an operation block. The register file is implemented using function generators configured as RAM blocks. This implementation eliminates the need for time-consuming accesses to an off-chip register file or to a dedicated RAM block.
REFERENCES:
patent: 5968161 (1999-10-01), Southgate
patent: 6434584 (2002-08-01), Henderson et al.
patent: 6775760 (2004-08-01), Shigeki
Xilinx; “Virtex -II Platform FPGA Handbook”; published Dec. 6, 2000; available from Xilinx, Inc.; 2100 Logic Drive, San Jose, California 95124; pp. 33-75.
Cartier Lois D.
Kim Kenneth S.
Maunu LeRoy D.
Xilinx , Inc.
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