Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-09-08
2003-03-18
Malzahn, David H. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S498000
Reexamination Certificate
active
06535900
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to accumulation saturation and more particularly to accumulation saturation in conjunction with a digital signal processor (DSP).
BACKGROUND OF THE INVENTION
Reference is now made to
FIG. 1A
which illustrates some of the main components of a digital signal processor
10
according to the prior art. DSP
10
is made up of a computation unit (CU)
12
connected to an accumulator
14
. Accumulator
14
is a storage element and is utilized for storing the result of an arithmetical or logical operation of CU
12
. The data stored within the accumulator
14
may, for example, be used as input data to CU
12
via a feedback loop or may be written to memory, as indicated.
The number of bits of information supported by CU
12
is a measure of the accuracy of DSP
10
, as it defines the dynamic range of the values that can be represented by DSP
10
. For example, 16 bits can represent a range of 0 to 2
16
−1 or alternatively a range of 2
15
−1 to −2
15
with one bit being utilized for the sign. The situation is similar with 32 bits. 32 bits can therefore represent a range of 0 to 2
32
−1 or 2
31
−1 to −2
31
.
FIG. 1A
illustrates CU
12
supporting an accuracy of 40 bits and accumulator
14
supporting an accuracy of 40 bits. It is usual for the accumulator
14
in a given DSP
10
to be chosen to be wider than the data width supported by DSP
10
for memory access. This allows the computations to be performed accurately whilst only the most significant portion of the result is used as the final result and written back to memory or to another device.
Different DSP
10
architectures exist; with different accumulator widths and standard algorithms which are strictly defined with a set of input and output vectors. This has led to a situation where a standard developed using a 32 bit accumulator DSP
10
, for example, yields different results or fails to meet the standard requirements when run on a DSP with a 40 bit accumulator which appears to have a larger accuracy. The DSP performance is thus degraded in terms of its accuracy in order for it to meet the requirements of a specific standard
FIG. 1A
illustrates a 40 bit accumulator
14
attached to a 40 bit CU
12
. In general, the accumulator width is W bits and the accuracy required (in order to meet the standard) is A bits. (where W is greater than A). The extra bits over and above those required are denoted E, where E=W−A. In the present example, DSP
10
has a 40 bit accumulator
14
(i.e W=40) and a 40 bit CU, but a limitation of accuracy is required to, for example, 32 bits (A=32) in order to meet the standard. This occurs when the standard only supports an accuracy of computation between CU
12
and accumulator
14
of 32 bits.
Reference is now made to
FIG. 1B
which illustrates a DSP
10
containing an exemplary mechanism for limiting the accuracy of computation between CU
12
and accumulator
14
according to the prior art. Similar items to those of previous figures have similar reference numbers and will not be described further. The method consists of inserting a saturation unit
16
between CU
12
and accumulator
14
in order to limit the accuracy of the computation to that required to correspond with the standard. Saturation unit
16
performs the operation of saturation (box
17
) when overflow (box
18
) is detected which means that the value leaving CU
12
is made up of more than 32 bits of information. Saturation is defined as the operation of clipping a value that cannot be represented in the exemplary required accuracy of 32 bits (i.e A=32) to the maximum or minimum value that can be represented in 32 bits. In other words, saturation is applied in case of 32 bit overflow. The value is thus limited to a value represented by 32 bits only, in the present example.
The computation is slower and less efficient due to the fact that the saturation check and substitution occurs on the path from the output of CU
12
to accumulator
14
. The check to detect overflow and the substitution of a saturated value between CU
12
and accumulator
14
delay the computation and therefore reduce the speed and hence the performance of the processor.
SUMMARY OF THE INVENTION
An object of the present invention is to provide saturation of values in a digital signal processor (DSP) with minimal degradation of processor performance.
A further object of the present invention is to provide means for saturating values in the feedback loop of a DSP between an accumulator and a computation unit and thus improving the speed of the processor.
There is thus provided, in accordance with a preferred embodiment of the present invention, a processor made up of a computation unit, an accumulator unit, a saturation determination unit and a saturation unit. The computation unit operates on one or more operands of W bits. The accumulator unit stores the output of the computation unit, in W bits. The saturation determination unit detects overflow in parallel with latching of the output of the computation unit. Overflow occurs when the operand latched by the accumulator represents a number having more than A significant bits, where A is less than W. The saturation unit provides saturation operands to the computation unit when the operand latched in the accumulator unit represents a number having more than A significant bits. Furthermore, the processor has saturation operands of either (+2
A−1
−1) or −2
A−1
.
There is further provided a method for providing saturated operands to a computation unit made up of the steps of latching an operand of W bits, detecting in parallel with the step of latching a condition and providing the computation unit with a saturated operand if the condition is met. The operand is initially received and latched by an accumulator from a computation unit. The condition detected is that the operand latched in the accumulator represents a number having more than A significant bits, where A is less than W. The saturation operand provided to the computation unit is the maximum positive or negative value which can be represented in A bits. Furthermore, the saturation operand provided to the computation unit is either (+2
A−1
−1) or −2
A−1
.
Further, there is provided a method for providing saturated operands in a feedback to a computation unit which entails providing a computation unit with a saturation operand. The computation unit is provided with a saturation operand if an operand stored in an accumulator represents a number with greater than A significant bits.
REFERENCES:
patent: 4223389 (1980-09-01), Amada et al.
patent: 5508951 (1996-04-01), Ishikawa
patent: 5847978 (1998-12-01), Ogura et al.
patent: 5936870 (1999-08-01), Im
patent: 5974540 (1999-10-01), Morikawa et al.
patent: 6321248 (2001-11-01), Bonnet et al.
Gross Yael
Perets Ronen
Sheier Moshe
DSP Group Ltd.
Eitan Pearl Latzer & Cohen-Zedek
Malzahn David H.
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