Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2002-10-02
2003-07-01
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S220000, C257S221000, C257S246000, C257S249000, C377S060000, C377S061000, C377S062000, C377S063000
Reexamination Certificate
active
06586784
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the field of charge-coupled devices and, more particularly, to such charge-coupled devices having substantially no capacitance when in the accumulation mode.
BACKGROUND OF THE INVENTION
As shown in
FIG. 1
, prior art charge-coupled devices
10
typically include a substrate or well
20
of the first conductivity type and buried channel
30
of the second conductivity type for the transfer of charge packets
40
. A plurality of gates
50
are separated from the buried channel
30
by a thin insulating layer
60
. For the purpose of illustration, it is assumed that the first conductivity type is p-type and the second conductivity type is n-type. The charge packets
40
are electrons flowing in the n-type buried channel
30
. The opposite type of the electron charge packets
40
will be holes flowing in the p-type substrate or well
20
.
Voltages applied to the gates
50
alter the potential energy within the buried channel
30
for the purpose of controlling the transfer of charge packets
40
through the charge-coupled device
10
. Additional p-type implants
70
are used to selectively alter the channel potential under the gates
50
for controlling the direction of charge packet
40
transfer.
If the CCD
10
is to be used as an imaging device, then the charge packets
40
transferred through the buried channel
30
were generated by photons. The photo-generated electrons in the charge packets
40
are called photoelectrons. In the case of full frame type image sensors, the photoelectrons are generated directly in the CCD. In the case of interline frame transfer image sensors, the photoelectrons are generated in photodiodes adjacent to the CCD. There are also undesired electrons generated in the charge packets by thermal processes. These thermally generated electrons degrade the charge packet signal quality. It is well known that the thermal generation rate of electrons may be reduced by maintaining the gates
50
at a negative voltage with respect to the well or substrate
20
. This causes holes to accumulate at the surface of the buried channel
30
. The abundance of holes at the surface suppresses the thermal generation of electrons. Gates
50
biased to maintain holes at the surface are said to be in accumulation. Gates
50
biased such that holes are not present at the surface are said to be in depletion. A description of the benefits of accumulation mode clocking of CCD's may be found in U.S. Pat. No. 4,963,952 by Janesick and in Solid-State Imaging with Charge-Coupled Devices by Albert J. P. Theuwissen.
In
FIG. 1
, at time T
1
all gate
50
voltages are at the low level which accumulates holes at the surface of the buried channel
30
. At time T
1
, the thermal generation of dark current is lowest. To move the charge packets
40
, the gates
50
must be clocked. The CCD shown in
FIG. 1
is a two phase CCD. It has two sets of gates, the first set
51
is clocked at voltage V
1
and the second set
52
is clocked at voltage V
2
. The clocking sequence of the voltages V
1
and V
2
are shown in FIG.
1
. It is well understood that CCDs may be fabricated with more than two sets of gates.
The gate
50
clocking scheme of U.S. Pat. No. 4,963,952 is sufficient for CCDs built in p-type substrates. The p-type substrate acts as a source or sink of holes as the gates
50
are clocked between accumulation and depletion voltages. However, as shown in
FIG. 2
many interline CCD image sensors are built on n-type substrates
100
with p-type wells
20
. The well
20
is confined in a narrow layer between the substrate
100
and buried channel
30
. Now the well
20
can not easily act as a source or sink of holes. When the gates
50
are clocked into accumulation, the holes must flow long distances from the well contact
110
at the perimeter of the CCD to the center of the CCD. The well
20
has a high resistance to the flow of holes. The nth gate
50
has a capacitance to the well
20
given by C
n
. The well
20
has a resistance from the well contact
110
to the nth gate given by R
n
. When the nth gate
50
is clocked into accumulation or depletion, the time it takes for holes to flow from the well contact
110
will be related to the product of C
n
R
n
. For large area CCDs, this time becomes so long that it limits the advantage of accumulation mode clocking.
One solution to this problem is described in U.S. Pat. No. 5,151,380. This patent discloses adding more well contacts
110
with a low resistance metal throughout the entire area of the CCD. While the low resistance metal would certainly speed up the flow of holes in and out of the well
20
, it adds significant complexity to the manufacturing process. The additional contacts
110
to the well
20
in close proximity to the CCD also introduces impurities to the buried channel
30
which increases the thermal generation of electrons. The presence of the low resistance metal may also block photons from reaching the photosensitive area of the CCD.
Consequently, it is clear that there is a need for a method of clocking a CCD in accumulation mode that does not require holes to travel long distances. In addition, it is also desirable for the method to apply to CCD's having more than two phases.
SUMMARY OF THE INVENTION
The present invention is directed to overcoming one or more of the problems set forth above. Briefly summarized, according to one aspect of the present invention, the invention resides in A method for reducing dark current within a charge coupled device comprising the steps of: (a) providing three or more phases of gates separated by an insulating layer from a buried channel of the first conductivity type in a well or substrate of the second conductivity type, and a clock driver for causing the transfer of charge through the charge coupled device; (b) providing a barrier for separating charge packets when in accumulation state; (c) applying, at a first time period, voltages to all phases of gates sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers; after the first time period, applying, at each gate phase n having a capacitance C
n
to the layer of the second conductivity type, a voltage change on the gate phase n given by &Dgr;V
n
such that the sum of products of the capacitances and voltage changes is substantially zero
∑
n
C
n
Δ
V
n
≅
0
;
and after the voltage changes required to transfer charge through the charge coupled device, returning the voltages of all phases of gates back to the voltage sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers.
These and other aspects, objects, features and advantages of the present invention will be more clearly understood and appreciated from a review of the following detailed description of the preferred embodiments and appended claims, and by reference to the accompanying drawings.
Advantageous Effect Of The Invention
The present invention has the advantage of reducing dark current, particularly in a three or more phase device, by enabling holes to flow more freely in accumulation without the need for additional contacts, which are undesirable as described hereinabove.
REFERENCES:
patent: 4709380 (1987-11-01), Itoh
patent: 4963952 (1990-10-01), Janesick
patent: 5151380 (1992-09-01), Hynecek
patent: 5521405 (1996-05-01), Nakashiba
patent: 5796801 (1998-08-01), Nakashiba
patent: 5986296 (1999-11-01), Caranhac et al.
patent: 6426238 (2002-07-01), Morimoto
Eastman Kodak Company
Ngo Ngan V.
Watkins Peyton C.
LandOfFree
Accumulation mode clocking of a charge-coupled device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Accumulation mode clocking of a charge-coupled device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Accumulation mode clocking of a charge-coupled device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3090711