Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2004-04-23
2004-11-30
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185270
Reexamination Certificate
active
06826084
ABSTRACT:
BACKGROUND
One of the primary goals of memory manufacturers is increasing the storage density of memory devices. Improvements in integrated circuit fabrication techniques can achieve this goal by reducing the sizes of integrated circuit structures. Accordingly, as fabrication techniques improve, manufacturers can often increase memory densities simply by making the same memory structures smaller. Another technique for improving storage density is improving the functionality of memory structures to provide more storage per area. This can be achieved, for example, by creating memory cells and peripheral memory circuits that are capable of storing more information per memory cell.
U.S. Pat. No. 6,011,725, entitled “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” describes a non-volatile memory that stores two bits per memory cell.
FIG. 1
shows a memory cell
100
such as described in U.S. Pat. No. 6,011,725. Memory cell
100
includes diffused N+ source/drain regions
120
A and
120
B in a silicon substrate
110
, a gate insulator
130
overlying substrate
110
, and a gate
150
overlying gate insulator
130
. Gate insulator
130
has an ONO structure including a silicon nitride region
140
sandwiched between silicon dioxide regions
132
and
134
.
Two bits of data are stored in memory cell
100
as charge that is trapped in separated and isolated locations
140
A and
140
B in nitride region
140
. Each location
140
A or
140
B corresponds to a bit having a value 0 or 1 according to the state of trapped charge at the location
140
A or
140
B. To program cell
100
, gate
150
is raised to a high voltage while a channel current passes between diffused regions
120
A and
120
B and injects charge into nitride region
140
. The location
140
A or
140
B of the injected charge depends on the characteristics of memory cell
100
, the applied voltages, and whether the channel current flows from region
120
A to region
120
B or from region
120
B to region
120
A. The direction of the channel current during a programming operation thus selects which of the bits (i.e., location
140
A or
140
B) is programmed.
Reading a data bit from a particular location
140
A or
140
B is accomplished by biasing gate
150
at a voltage that is above the threshold voltage of memory cell
100
when locations
140
A and
140
B are in an unprogrammed state. The diffused region
120
A or
120
B that is closest to the location
140
A or
140
B being read is biased as the source/region for the read operation. Any charge trapped in locations
140
A and
140
B affects a portion of the underlying channel so that negative charge trapped near the source effectively reduces the gate-to-source voltage and correspondingly reduces the channel current during the read operation. In contrast, negative charge near the drain region is ineffective at reducing the channel current since an appropriate drain voltage effectively punches through the portion of the channel near the drain. Sensing whether a channel current flows in memory cell
100
during the read indicates the value of the bit associated with the location
140
A or
140
B nearest the source/region
120
A or
120
B.
Memory cell
100
has the advantage of providing non-volatile storage of two bits of information in a single-transistor memory cell, increasing the storage density when compared to a memory device storing one bit of data per storage transistor. However, scaling memory cell
100
down to smaller feature sizes may present difficulties. In particular, operation of memory cell
100
requires the ability to inject charge into separate locations
140
A and
140
B in nitride region
140
. As the size of nitride region
140
decreases, the shorter distance between locations
140
A and
140
B may be unable to accommodate lateral charge movement after the write operation. Additionally, the amount of charge trapped at locations
140
A and
140
B of nitride region
140
is relatively small (e.g., typically a few hundred electrons) when compared, for example, to the charge (e.g., typically tens of thousands of electrons) in the floating gate of a conventional Flash memory cell. The smaller trapped charge makes precise control of threshold voltages more difficult because small variations in the trapped charge have large effects. This renders analog or multi-bit storage at each location
140
A or
140
B in memory cell
100
substantially more difficult than analog or multi-bit storage in a conventional Flash memory cell.
SUMMARY
In accordance with an aspect of the invention, a memory transistor has two laterally separated floating gates over a channel. A control gate that overlies the floating gates extends into a gap between the floating gates to directly modulate a central channel portion between the floating gates. The memory transistor can store separate data values as charge on the separate floating gates. The threshold voltage of the memory transistor depends on the charge stored on the floating gates and the direction of the channel current. Since the amount of charge that can be stored on each floating gate is relatively large compared to charge that can be trapped in a gate insulator, the amounts of stored charge and the threshold voltages of the dual-floating-gate memory transistor can be controlled more precisely than is possible in some known memory devices that store data as locally trapped charge. The control gate directly modulating the central channel region shuts off the current through unselected memory transistors, which permits “over-erasing” the floating gates to extend the usable threshold voltage range for storing data. The improved control of the threshold voltage and the larger available threshold voltage range facilitates reliable storage of multiple levels or multiple bits of data in each floating gate.
In accordance with a further aspect of the invention, the memory transistor having laterally separated floating gates uses holes in the floating gates to define the charge states representing data values. Charge states arising from holes on a floating gate are known to provide better data stability. The holes cause channel regions under the floating gate to have low or negative threshold voltages, while the central channel region, which the control gate modules, has a positive threshold voltage. Accordingly, the memory transistor is off when the control gate is grounded, but a read operation that biases the control gate to a level sufficient for charge inversion in the central channel region can compare the amount of current through a memory transistor to a reference current to determine a stored data value.
One specific embodiment of the invention is a device containing an array of memory transistors. Each memory transistor includes: a first source/drain region, a second source/drain region, and a channel in a substrate; a first floating gate overlying a first end of the channel adjacent the first source/drain region; a second floating gate overlying a second end of the channel adjacent the second source/drain region; and a control gate overlying the first and second floating gates and extending into the gap between the first and second floating gates. The first and second source/drain regions can extend under part of the first and second floating gates, respectively, to reduce the effective channel lengths under the first and second floating gates and improve the selectivity and precision of writing and reading stored data values associated with the floating gates.
In contactless, virtual ground architecture, the array includes multiple banks. Each bank includes diffused lines in the substrate, and each column of the memory transistors in the bank corresponds to and connects to an adjacent pair of the diffused lines. A first of the corresponding diffused lines electrically connects the first source/drain regions of the memory transistor in the row, and a second of the corresponding diffused lines electrically connects the second source/drain regi
Lebentritt Michael S.
Millers David T.
Multi Level Memory Technology
Nguyen Hien
LandOfFree
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