Access structure for high density read only memory

Details Access structure for high density read only memory Access structure for high density read only memory

2000-06-05

2001-09-18

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read only systems

C365S051000

Reexamination Certificate

active

06292384

ABSTRACT:

TECHNICAL FIELD
This invention relates to the read only memory structures, and more particularly, the arrangement of circuitry for reducing the area required to access a high density read only memory.
BACKGROUND OF THE INVENTION
A well known problem in the art of read only memories is that the circuitry required to access, i.e., to address and read the memory, requires area on the memory chip, because the memory cells are read using decoders and selectors located on the periphery of the memory array. According to the prior art, the more dense the memory array, the more area required for the decoders and selectors relative to the memory array area. As a result, for a very high density memory array, such as is disclosed in U.S. patent application Ser. No. 08/748,035, now U.S. Pat. No. 5,847,442 which is assigned to the same assignee as the present invention and is incorporated by reference as if set forth fully herein, it is impractical to use prior art access techniques, because the area overhead required for the decoders and selectors essentially negates the advantage of the increased memory density.
SUMMARY OF THE INVENTION
I have recognized that the problems with accessing high density read only memory arrays can be avoided, in accordance with the principles of the invention, by placing the decoders and selectors which are used to access the read only memory array in another layer which is above and/or below the read only memory array layers. Note that by layer it is meant a substantially planar structure with some thickness in which the circuitry that makes up particular functionality resides. Thus, the inefficient two-dimensional structure of the prior art is folded over to create a compact read only memory device with a three-dimensional structure. In accordance with an aspect of the invention, connection of the decoders to the rows is not limited to the ends of the rows, but instead may be made at any point along the rows. Similarly, connection of the selectors to the columns is not limited to the ends of the columns, but instead may be made at any point along the columns. Advantageously, additional circuitry is not required on the periphery of the memory array, so that a smaller overall memory device is achieved. In addition, in order to reduce cross talk when reading the memory array with a low impedance amplifier, the memory is addressed using a single active row, and, in accordance with an aspect of the invention, it is read only one column at a time.


REFERENCES:
patent: 4736342 (1998-04-01), Imondi
patent: 5408428 (1995-04-01), Burgess
patent: 5432730 (1995-07-01), Shubat
patent: 5835396 (1998-12-01), Zhang
patent: 5847442 (1998-12-01), Mills

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