Access request prioritization and summary device

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Details

3642426, 3642412, 364DIG1, 36494191, 364DIG2, G06F 1337

Patent

active

052029999

ABSTRACT:
An access request prioritization and summary device for determining the current highest priority among n entities. The device includes a bitmap having n bit storage locations. Each one of the n bit storage locations corresponds to one of the entities and is used to store a value which represents when the corresponding entity is available for prioritization. A plurality of combinational logic blocks are connected to the bitmap so that each one of the combinational logic blocks receives a preselected portion of the values stored in the n bit storage locations of the bitmap. Each one of the combinational logic blocks has a token signal input and a token signal output. The token signal inputs and outputs are coupled together to form a series of token signal links between the combinational logic blocks. When certain preselected highest priority determination conditions occur within one of the combinational logic blocks, the combinational logic block generates a token signal which serves as the token signal to the respective succeeding combinational logic block. Each combinational logic block is capable of receiving a token signal from the previous combinational logic block and is responsive to the input of a token signal to determine a current highest priority from the values which it received as input signals.

REFERENCES:
patent: 3599162 (1971-08-01), Byrns
patent: 4148011 (1979-04-01), McLagan et al.
patent: 4326249 (1982-04-01), Godsey
patent: 4365294 (1982-12-01), Stokken
patent: 4380052 (1983-04-01), Shima
patent: 4621342 (1986-11-01), Capizzi et al.
patent: 4630041 (1986-12-01), Casamatta et al.
patent: 4660169 (1987-04-01), Norgen et al.
Mano, "Computer System Architecture", 2nd ed., 1982, pp. 434-437.

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