Access of two synchronous busses with asynchronous clocks to...

Details Access of two synchronous busses with asynchronous clocks to... Access of two synchronous busses with asynchronous clocks to...

2007-01-30

2007-01-30

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189020

Reexamination Certificate

active

10869484

ABSTRACT:
A method and circuit are provided for controlling access of two synchronous busses with asynchronous clocks to a synchronous single port Random Access Memory (RAM). In one preferred method, the clock of bus A is switched off via a control flip-flop and then the clock of bus B is switched on, allowing the control and data signals to pass through simple multiplexers. Bus B becomes the owner of the RAM. Later, the clock of bus B is switched off via the control flip-flop and then clock of bus A is switched on, such that bus A becomes owner of the bus. This allows any relative speed between the bus clocks.

REFERENCES:
patent: 5422858 (1995-06-01), Mizukami et al.
patent: 6078527 (2000-06-01), Roth et al.
patent: 6229741 (2001-05-01), Maeno
patent: 6683818 (2004-01-01), Cornell et al.

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