Access network for addressing subwords in memory for both little

Details Access network for addressing subwords in memory for both little Access network for addressing subwords in memory for both little

1997-12-03

1999-06-29

Lim, Krisna

395886, G06F 1300

Patent

active

059180757

ABSTRACT:
The access network selects 2.sup.m byte-size subwords for little or big endian byte order from a 2.sup.n byte-sized memory word with 0.ltoreq.m.ltoreq.n. The access network includes 2.sup.n 2.sup.n :1 multiplexers and a device for generating control signals for the multiplexers. The control signal for the multiplexer for the ith byte is formed by inverting or copying address bits above alignment of the subword for the multiplexer selecting the ith byte with the least address, byte 0, and by setting address bits below alignment of the subword to 0 or 1 for big or little endian byte order. The device for generating the control signals generates the control signal for the multiplexer for the byte i with an exclusive "or" of the subword address i with the control signal for byte 0. By using common parts space can be saved in the access network.

REFERENCES:
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patent: 5477543 (1995-12-01), Purcell
patent: 5524256 (1996-06-01), Turkowski
patent: 5655065 (1997-08-01), Robertson
patent: 5687328 (1997-11-01), Lee
patent: 5721957 (1998-02-01), Huang et al.

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