Access control system for multi-banked DRAM memory

Details Access control system for multi-banked DRAM memory Access control system for multi-banked DRAM memory

2001-10-05

2004-01-27

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S233100

Reexamination Certificate

active

06683816

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the control of memory systems. More specifically, the invention relates to controlling access to banked dynamic random access memory (DRAM) systems.
BACKGROUND
Banked DRAM Memory Systems. A particular row in a DRAM is commonly referred to as a “page” of memory. Generally speaking, an individual memory location may be specified using a row address and a column address. In older DRAM systems, only one page could be active at any given time. It was soon realized that multiple DRAM chips could be organized into “banks” so that more than one page could be active at a time—one active page per bank. It is now common to organize the pages of a single DRAM memory device into several banks internally. Multi-bank memory systems may also be formed using chips that have multiple banks internally. In any of these kinds of multiple-bank systems, a bank address is needed in addition to a row address and column address to specify a single memory location.
Bank/Row Activation Dead Time. Prior to accessing a target memory location in any multi-bank DRAM system, the corresponding page must first be activated. In other words, the bank/row combination in which the target memory location resides must be activated. After the bank/row activation step has been completed, efficiency may be achieved by performing multiple accesses on columns within the activated bank/row. Even more efficiency may be achieved if the multiple accesses are performed using “burst” commands, which are specifically designed to access sequential columns within a single bank/row. Prior to activating and accessing a different row within the same bank, the previously-accessed bank must be precharged. The precharge step is commonly referred to as “closing” a bank/row within the DRAM.
Each time an activate or precharge command is executed on a given bank, a certain amount of dead time is encountered before memory accesses can be performed on that bank. For example, after a bank/row activate command is issued to the DRAM chip, the memory controller must wait a predetermined minimum time prior to issuing reads or writes to column addresses within the activated bank/row. Similarly, the memory controller must wait a predetermined minimum time after issuing a precharge command to a bank before issuing an activate command to the same bank. The dead time that results from performing bank/row activates and precharges on the DRAM can dramatically affect the bandwidth that is available for executing memory accesses. For this reason, one of the concerns in memory controller design is to determine when precharge commands should be issued to the DRAM.
SUMMARY OF THE INVENTION
In one aspect, the invention includes a method and apparatus for controlling access to a multi-bank DRAM memory system. Multiple unexecuted bank/row activation requests are presented simultaneously by various processes or systems seeking access to the memory system. According to first criteria, one of the banks of the memory system is selected to be the target of a next bank/row activation request. According to second criteria, one of the unexecuted bank/row activation requests corresponding to the chosen bank is selected and issued as the next bank/row activation request.
In another aspect, the first criteria may include selecting the most recently used bank if to do so will likely result in the next bank/row activation request being processed before a precharge command is issued in relation to an immediately preceding bank/row activation request. In this manner, a precharge/activate pair may be eliminated from the command stream, thus conserving memory access bandwidth. Otherwise, the first criteria may include selecting the least recently used bank that corresponds to one of the unexecuted bank/row activation requests. Such a selection maximizes the opportunity to issue precharge and activate commands to the newly selected bank while burst activity is occurring in a previously-selected bank, again conserving memory access bandwidth.
In another aspect, the second criteria may include selecting a bank/row activation request whose target row is the same as a currently active row in the request's target bank. In this manner, a precharge/activate pair may be eliminated from the command stream, thus conserving memory access bandwidth. Otherwise, the second criteria may include selecting a bank/row activation request according to a predetermined ranking of the sources that generate the requests.
In another aspect, the invention includes iteratively and conditionally selecting unexecuted bank/row activation requests until a request is found whose target row is the same as a currently active row in the request's target bank. The iterative nature of the selection process, performed over several clock states, allows for the possibility of new and superior candidates for selection becoming available during the selection procedure. It also allows a single comparator to be used during the comparison and selection process.
In another aspect, the invention includes apparatus for controlling access to a DRAM memory system having multiple banks. The apparatus may include a multiplexer having its data inputs coupled to unexecuted bank/row activation requests; a bank selection system operable to choose one of the multiple banks of the memory system to be the target of a next bank/row activation request; and a stream selection system operable to choose one of the unexecuted bank/row activation requests corresponding to the chosen bank and to select the chosen request at the output of the multiplexer.
In another aspect, an apparatus for controlling access to a DRAM memory system having multiple banks may include storage logic operable to store plural unexecuted bank/row activation requests; and selection logic having at least one input coupled to the storage logic and having an output for presenting bank/row activation requests for execution. The selection logic may be operable: to conditionally choose a first one of the stored plural requests for possible execution; to determine whether the first conditionally chosen request meets certain criteria; and if so, to present the first conditionally chosen request for execution; but if not, to conditionally choose a second one of the stored plural requests for possible execution.
In still another aspect, the invention includes program code for causing a computer to control access to a multi-bank memory system in accordance with the above-described methods and apparatus.


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